Datasheet
REV. A
ADuC834
–11–
PIN FUNCTION DESCRIPTIONS (continued)
Pin No. Pin No.
52-Lead 56-Lead
MQFP CSP Mnemonic
Type*
Description
3–4, 2–3, P1.2–P1.7 I Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital
9–12 11–14 input for which ‘0’ must be written to the port bit. As a digital input, these pins
must be driven high or low externally.
These pins also have the following analog functionality:
P1.2/DAC/IEXC1 I/O The voltage output from the DAC or one or both current sources (200 A or
2 200 A) can be configured to appear at this pin.
P1.3/AIN5/IEXC2 I/O Auxiliary ADC Input or one or both current sources can be configured at this pin.
P1.4/AIN1 I Primary ADC, Positive Analog Input
P1.5/AIN2 I Primary ADC, Negative Analog Input
P1.6/AIN3 I Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input
P1.7/AIN4/DAC I/O Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input. The voltage
output from the DAC can also be configured to appear at this pin.
5 4, 5 AV
DD
SAnalog Supply Voltage, 3 V or 5 V
6 6, 7, 8 AGND S Analog Ground. Ground reference pin for the analog circuitry.
79REFIN(–) I Reference Input, Negative Terminal
810REFIN(+) I Reference Input, Positive Terminal
13 15 SS I Slave Select Input for the SPI Interface. A weak pull-up is present on this pin.
14 16 MISO I/O Master Input/Slave Output for the SPI Interface. There is a weak pull-up on this
input pin.
15 17 RESET I Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is
running resets the device. There is an internal weak pull-down and a Schmitt
trigger input stage on this pin.
16–19, 18–21, P3.0–P3.7 I/O Bidirectional port pins with internal pull-up resistors. Port 3 pins that have 1s written
22–25 24–27 to them are pulled high by the internal pull-up resistors, and in that state can be used
as inputs. As inputs, Port 3 pins being pulled externally low will source current
because of the internal pull-up resistors. When driving a 0-to-1 output transition,
a strong pull-up is active for two core clock periods of the instruction cycle.
Port 3 pins also have various secondary functions including:
P3.0/RXD I/O Receiver Data for UART Serial Port
P3.1/TXD I/O Transmitter Data for UART Serial Port
P3.2/INT0 I/O External Interrupt 0. This pin can also be used as a gate control input to Timer 0.
P3.3/INT1 I/O External Interrupt 1. This pin can also be used as a gate control input to Timer 1.
P3.4/T0/ I/O Timer/Counter 0 External Input. If the PWM is enabled, an external clock may be
PWMCLK input at this pin.
P3.5/T1 I/O Timer/Counter 1 External Input
P3.6/WR I/O External Data Memory Write Strobe. Latches the data byte from Port 0 into an
external data memory.
P3.7/RD I/O External Data Memory Read Strobe. Enables the data from an external data
memory to Port 0.
20, 34, 48 22, 36, 51
DV
DD
SDigital Supply, 3 V or 5 V.
21, 35, 23, 37, DGND S Digital Ground. Ground reference point for the digital circuitry.
47 38, 50
26 SCLOCK I/O Serial Interface Clock for Either the I
2
C or SPI Interface. As an input, this pin is a
Schmitt-triggered input and a weak internal pull-up is present on this pin unless
it is outputting logic low. This pin can also be directly controlled in software as a
digital output pin.
27 MOSI/SDATA I/O Serial Data I/O for the I
2
C Interface or Master Output/Slave Input for the SPI
Interface. A weak internal pull-up is present on this pin unless it is outputting logic
low. This pin can also be directly controlled in software as a digital output pin.