Datasheet

Data Sheet ADuC832
Rev. B | Page 83 of 92
LATCH
SRAM
A8 TO A15
A0 TO A7
D0 TO D7
(DATA)
ADuC832
P2
ALE
P0
02987-076
RD
WR
OE
WE
Figure 88. External Data Memory Interface (64 kB Address Space)
If access to more than 64 kB of RAM is desired, a feature unique
to the ADuC832 allows addressing up to 16 MB of external
RAM simply by adding an additional latch, as illustrated in
Figure 89.
LATCH
ADuC832
RD
P2
ALE
P0
WR
LATCH
SRAM
OE
A8 TO A15
A0 TO A7
D0 TO D7
(DATA)
WE
A16 TO A23
0
2987-077
Figure 89. External Data Memory Interface (16 MB Address Space)
In either implementation, Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the data pointer (DPL)
as an address, which is latched by a pulse of ALE prior to data
being placed on the bus by the ADuC832 (write operation) or
the SRAM (read operation). Port 2 (P2) provides the data
pointer page byte (DPP) to be latched by ALE, followed by the
data pointer high byte (DPH). If no latch is connected to P2,
DPP is ignored by the SRAM, and the 8051 standard of 64 kB
external data memory access is maintained.
POWER SUPPLIES
The ADuC832 operational power supply voltage range is 2.7 V
to 5.25 V. Although the guaranteed data sheet specifications are
given only for power supplies within 2.7 V to 3.6 V or 10% of
the nominal 5 V level, the chip functions equally well at any
power supply level between 2.7 V and 5.5 V.
Note that Figure 90 and Figure 91 refer to the MQFP package.
For the LFCSP package, connect the extra DV
DD
, DGND, AV
DD
,
and AGND in the same manner.
Separate analog and digital power supply pins (AV
DD
and DV
DD
,
respectively) allow AV
DD
to be relatively free of noisy digital signals
often present on the system DV
DD
line. However, though AV
DD
and DV
DD
can be powered from two separate supplies if desired,
they must remain within 0.3 V of one another at all times to
avoid damaging the chip (as per the Absolute Maximum Ratings
section). Therefore, it is recommended that, unless AV
DD
and
DV
DD
are connected directly together, back-to-back Schottky
diodes be connected between them as shown in Figure 90.
DV
DD
ADuC832
AGND
AV
DD
0.1µF
0.1µF
10µF
ANALOG SUPPLY
10µF
DGND
DIGITAL SUPPLY
02987-078
Figure 90. External Dual-Supply Connections
As an alternative to providing two separate power supplies,
the user can keep AV
DD
quiet by placing a small series resistor
and/or ferrite bead between it and DV
DD
, and then decoupling
AV
DD
separately to ground. An example of this configuration is
shown in Figure 91. With this configuration, other analog circuitry
(such as op amps and voltage reference) can be powered from
the AV
DD
supply line as well. The user should still include back-
to-back Schottky diodes between AV
DD
and DV
DD
to protect
from power-up and power-down transient conditions that may
separate the two supply voltages momentarily.
10µF
10µF
DV
DD
ADuC832
AGND
DGND
0.1µF
0.1µF
DIGITAL SUPPLY
1.6Ω
BEAD
AV
DD
0
2987-079
Figure 91. External Single-Supply Connections
Note that, in both Figure 90 and Figure 91, a large value (10 μF)
reservoir capacitor is connected to DV
DD
and a separate 10 μF
capacitor is connected to AV
DD
. Also, local small-value (0.1 μF)
capacitors are located at each AV
DD
pin of the chip. As per stan-
dard design practice, be sure to include all of these capacitors,
and ensure that the smaller capacitors are close to each AV
DD
pin with trace lengths as short as possible. Connect the ground
terminal of each of these capacitors directly to the underlying
ground plane. Finally, it should also be noted that, at all times,
the analog and digital ground pins on the ADuC832 must be
referenced to the same system ground reference point.