Datasheet

Data Sheet ADuC832
Rev. B | Page 81 of 92
INTERRUPT PRIORITY
The interrupt enable registers are written by the user to enable
individual interrupt sources, whereas the interrupt priority
registers allow the user to select one of two priority levels for
each interrupt. An interrupt of a high priority may interrupt the
service routine of a low priority interrupt, and if two interrupts
of different priority occur at the same time, the higher level
interrupt is serviced first. An interrupt cannot be interrupted by
another interrupt of the same priority level. If two interrupts of
the same priority level occur simultaneously, a polling sequence
is observed, as shown in Table 48.
Table 48. Priority Within an Interrupt Level
Source Priority Description
PSMI 1 (highest) Power supply monitor interrupt
WDS 2 Watchdog timer interrupt
IE0 2 External Interrupt 0
ADCI 3 ADC interrupt
TF0
4
Timer/Counter 0 interrupt
IE1 5 External Interrupt 1
TF1 6 Timer/Counter 1 interrupt
ISPI/I2CI 7 SPI Interrupt/I
2
C interrupt
RI + TI 8 Serial interrupt
TF2 + EXF2 9 (lowest) Timer/Counter 2 interrupt
TII 11 (lowest) Time interval counter interrupt
INTERRUPT VECTORS
When an interrupt occurs, the program counter is pushed onto
the stack and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in Table 49.
Table 49. Interrupt Vector Addresses
Source Vector Address
IE0 0003H
TF0 000BH
IE1 0013H
TF1
001BH
RI + TI 0023H
TF2 + EXF2 002BH
ADCI 0033H
ISPI/I2CI 003BH
PSMI 0043H
TII 0053H
WDS 005BH