Datasheet

ADuC832 Data Sheet
Rev. B | Page 80 of 92
INTERRUPT SYSTEM
The ADuC832 provides a total of nine interrupt sources with
two priority levels. The control and configuration of the inter-
rupt system is carried out through three interrupt-related SFRs:
• IE—interrupt enable register
• IP—interrupt priority register
• IEIP2—secondary interrupt enable register
IE (INTERRUPT ENABLE REGISTER)
SFR Address: A8H
Power-On Default Value: 00H
Bit Addressable: Ye s
Table 45. IE SFR Bit Designations
Bit Name Description
[7]
EA
Written by user to enable or disable all interrupt sources (1 = enable; 0 = disable)
[6] EADC Written by user to enable or disable ADC interrupt (1 = enable; 0 = disable)
[5] ET2 Written by user to enable or disable Timer 2 interrupt (1 = enable; 0 = disable)
[4] ES Written by user to enable or disable UART serial port interrupt (1 = enable; 0 = disable)
[3] ET1 Written by user to enable or disable Timer 1 interrupt (1 = enable; 0 = disable)
[2] EX1 Written by user to enable or disable External Interrupt 1 (1 = enable; 0 = disable)
[1] ET0 Written by user to enable or disable Timer 0 interrupt (1 = enable; 0 = disable)
[0] EX0 Written by user to enable or disable External Interrupt 0 (1 = enable; 0 = disable)
IP (INTERRUPT PRIORITY REGISTER )
SFR Address: B8H
Power-On Default Value: 00H
Bit Addressable: Ye s
Table 46. IP SFR Bit Designations
Bit Name Description
[7] Reserved Reserved for future use.
[6] PADC Written by user to select ADC interrupt priority (1 = high; 0 = low)
[5] PT2 Written by user to select Timer 2 interrupt priority (1 = high; 0 = low)
[4] PS Written by user to select UART serial port interrupt priority (1 = high; 0 = low)
[3] PT1 Written by user to select Timer 1 interrupt priority (1 = high; 0 = low)
[2] PX1 Written by user to select External Interrupt 1 priority (1 = high; 0 = low)
[1] PT0 Written by user to select Timer 0 interrupt priority (1 = high; 0 = low)
[0] PX0 Written by user to select External Interrupt 0 priority (1 = high; 0 = low)
IEIP2 (SECONDARY INTERRUPT ENABLE REGISTER)
SFR Address A9H
Power-On Default Value A0H
Bit Addressable No
Table 47. IEIP2 SFR Bit Designations
Bit
Name
Description
[7] Reserved Reserved for future use
[6]
PTI
Priority for time interval interrupt
[5] PPSM Priority for power supply monitor interrupt
[4] PSI Priority for SPI/I
2
C interrupt
[3] Reserved This bit must contain 0.
[2] ETI Written by user to enable or disable time interval counter interrupt. (1 = enable; 0 = disable)
[1] EPSMI Written by user to enable or disable power supply monitor interrupt. (1 = enable; 0 = disable)
[0]
ESI
Written by user to enable or disable SPI or I
2
C serial port interrupt. (1 = enable; 0 = disable)