Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Explanation of Typical Performance Plots
- Memory Organization
- Special Function Registers (SFRs)
- Special Function Registers
- ADC Circuit Information
- Calibrating the ADC
- Initiating Calibration in Code
- Nonvolatile Flash/EE Memory
- Using the Flash/EE Data Memory
- User Interface to Other On-Chip ADuC832 Peripherals
- On-Chip PLL
- Pulse-Width Modulator (PWM)
- PWM Modes of Operation
- Serial Peripheral Interface
- I2C-Compatible Interface
- Dual Data Pointers
- Power Supply Monitor
- Watchdog Timer
- Time Interval Counter (TIC)
- 8052-Compatible On-Chip Peripherals
- Timer/Counter 0 And Timer/Counter 1 Operating Modes
- Timer/Counter 2
- UART Serial Interface
- SBUF
- SCON (UART Serial Port Control Register)
- Mode 0: 8-Bit Shift Register Mode
- Mode 1: 8-Bit UART, Variable Baud Rate
- Mode 2: 9-Bit UART with Fixed Baud Rate
- Mode 3: 9-Bit UART with Variable Baud Rate
- UART Serial Port Baud Rate Generation
- Timer 1 Generated Baud Rates
- Timer 2 Generated Baud Rates
- Timer 3 Generated Baud Rates
- Interrupt System
- ADuC832 Hardware Design Considerations
- Other Hardware Considerations
- Development Tools
- Outline Dimensions
ADuC832 Data Sheet
Rev. B | Page 8 of 92
Parameter
1
V
DD
= 5 V V
DD
= 3 V Unit Test Conditions/Comments
SCLOCK and RESET ONLY
4
(Schmitt-Triggered Inputs)
V
T+
1.3 0.95 V min
3.0 2.5 V max
V
T−
0.8 0.4 V min
1.4 1.1 V max
V
T+
− V
T−
0.3 0.3 V min
0.85 0.85 V max
CRYSTAL OSCILLATOR
Logic Inputs, XTAL1 Only
V
INL
, Input Low Voltage 0.8 0.4 V typ
V
INH
, Input High Voltage 3.5 2.5 V typ
XTAL1 Input Capacitance 18 18 pF typ
XTAL2 Output Capacitance 18 18 pF typ
MCU CLOCK RATE 16.78 16.78 MHz max Programmable via PLLCON[2:0]
DIGITAL OUTPUTS
Output High Voltage (V
OH
)
2.4
V min
V
DD
= 4.5 V to 5.5 V
4.0 V typ I
SOURCE
= 80 μA
2.4 V min V
DD
= 2.7 V to 3.3 V
2.6 V typ I
SOURCE
= 20 μA
Output Low Voltage (V
OL
)
ALE, Port 0 and Port 2 0.4 0.4 V max I
SINK
= 1.6 mA
0.2 0.2 V typ I
SINK
= 1.6 mA
Port 3 0.4 0.4 V max I
SINK
= 4 mA
SCLOCK/SDATA 0.4 0.4 V max I
SINK
= 8 mA, I
2
C enabled
Floating State Leakage Current
4
±10 ±10 μA max
±1 ±1 μA typ
Floating State Output Capacitance 10 10 pF typ
START-UP TIME At any Core_CLK
At Power-On 500 500 ms typ
From Idle Mode 100 100 μs typ
From Power-Down Mode
Wakeup with
INT0
Interrupt
150 400 μs typ
Wakeup with SPI/I
2
C Interrupt 150 400 μs typ
Wakeup with External Reset 150 400 μs typ
After External Reset in Normal Mode 30 30 ms typ
After WDT Reset in Normal Mode 3 3 ms typ Controlled via WDCON SFR
POWER REQUIREMENTS
19, 20
Power Supply Voltages
AV
DD
/DV
DD
− AGND 2.7 V min AV
DD
/DV
DD
= 3 V nom
3.3 V max
4.5 V min AV
DD
/DV
DD
= 5 V nom
5.5 V max
Power Supply Currents Normal Mode
DV
DD
Current
4
6 3 mA max Core_CLK = 2.097 MHz
AV
DD
Current 1.7 1.7 mA max Core_CLK = 2.097 MHz
DV
DD
Current 23 12 mA max Core_CLK = 16.78 MHz
20
10
mA typ
Core_CLK = 16.78 MHz
AV
DD
Current 1.7 1.7 mA max Core_CLK = 16.78 MHz
Power Supply Currents Idle Mode
DV
DD
Current 4 2 mA typ Core_CLK = 2.097 MHz
AV
DD
Current 0.14 0.14 mA typ Core_CLK = 2.097 MHz
DV
DD
Current
4
10 5 mA max Core_CLK = 16.78 MHz
9 4 mA typ Core_CLK = 16.78 MHz
AV
DD
Current 0.14 0.14 mA typ Core_CLK = 16.78 MHz