Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Explanation of Typical Performance Plots
- Memory Organization
- Special Function Registers (SFRs)
- Special Function Registers
- ADC Circuit Information
- Calibrating the ADC
- Initiating Calibration in Code
- Nonvolatile Flash/EE Memory
- Using the Flash/EE Data Memory
- User Interface to Other On-Chip ADuC832 Peripherals
- On-Chip PLL
- Pulse-Width Modulator (PWM)
- PWM Modes of Operation
- Serial Peripheral Interface
- I2C-Compatible Interface
- Dual Data Pointers
- Power Supply Monitor
- Watchdog Timer
- Time Interval Counter (TIC)
- 8052-Compatible On-Chip Peripherals
- Timer/Counter 0 And Timer/Counter 1 Operating Modes
- Timer/Counter 2
- UART Serial Interface
- SBUF
- SCON (UART Serial Port Control Register)
- Mode 0: 8-Bit Shift Register Mode
- Mode 1: 8-Bit UART, Variable Baud Rate
- Mode 2: 9-Bit UART with Fixed Baud Rate
- Mode 3: 9-Bit UART with Variable Baud Rate
- UART Serial Port Baud Rate Generation
- Timer 1 Generated Baud Rates
- Timer 2 Generated Baud Rates
- Timer 3 Generated Baud Rates
- Interrupt System
- ADuC832 Hardware Design Considerations
- Other Hardware Considerations
- Development Tools
- Outline Dimensions

Data Sheet ADuC832
Rev. B | Page 73 of 92
TIMER/COUNTER 2
T2CON (TIMER/COUNTER 2 CONTROL REGISTER)
SFR Address: C8H
Power-On Default Value: 00H
Bit Addressable: Ye s
TIMER/COUNTER 2 DATA REGISTERS
Timer/Counter 2 also has two pairs of 8-bit data registers
associated with it. These are used as both timer data registers
and timer capture/reload registers.
TH2 and TL2
TH2 is the Timer 2 data high byte and TL2 is the low byte. The
SFR addresses for TH2 and TL2 are CDH and CCH, respectively.
RCAP2H and RCAP2L
RCAP2H is the Timer 2 capture/reload high byte and RCAP2L
is the low byte. The SFR addresses for RCAP2H and RCAP2L
are CBH and CAH, respectively.
Table 38. T2CON SFR Bit Designations
Bit Name Description
[7] TF2
Timer 2 overflow flag.
Set by hardware on a Timer 2 overflow. TF2 is not set when either RCLK = 1 or TCLK = 1.
Cleared by user software.
[6] EXF2
Timer 2 external flag.
Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
Cleared by user software.
[5] RCLK
Receive clock enable bit.
Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port Mode 1 and Mode 3.
Cleared by the user to enable Timer 1 overflow to be used for the receive clock.
[4]
TCLK
Transmit clock enable bit.
Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Mode 1 and
Mode 3. Cleared by the user to enable Timer 1 overflow to be used for the transmit clock.
[3] EXEN2
Timer 2 external enable flag.
Set by the user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used
to clock the serial port.
Cleared by the user for Timer 2 to ignore events at T2EX.
[2] TR2
Timer 2 start/stop control bit.
Set by the user to start Timer 2.
Cleared by the user to stop Timer 2.
[1] CNT2
Timer 2 timer or counter function select bit.
Set by the user to select counter function (input from external T2 pin).
Cleared by the user to select timer function (input from on-chip core clock).
[0] CAP2
Timer 2 capture/reload select bit.
Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1.
Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When
either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow.