Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Explanation of Typical Performance Plots
- Memory Organization
- Special Function Registers (SFRs)
- Special Function Registers
- ADC Circuit Information
- Calibrating the ADC
- Initiating Calibration in Code
- Nonvolatile Flash/EE Memory
- Using the Flash/EE Data Memory
- User Interface to Other On-Chip ADuC832 Peripherals
- On-Chip PLL
- Pulse-Width Modulator (PWM)
- PWM Modes of Operation
- Serial Peripheral Interface
- I2C-Compatible Interface
- Dual Data Pointers
- Power Supply Monitor
- Watchdog Timer
- Time Interval Counter (TIC)
- 8052-Compatible On-Chip Peripherals
- Timer/Counter 0 And Timer/Counter 1 Operating Modes
- Timer/Counter 2
- UART Serial Interface
- SBUF
- SCON (UART Serial Port Control Register)
- Mode 0: 8-Bit Shift Register Mode
- Mode 1: 8-Bit UART, Variable Baud Rate
- Mode 2: 9-Bit UART with Fixed Baud Rate
- Mode 3: 9-Bit UART with Variable Baud Rate
- UART Serial Port Baud Rate Generation
- Timer 1 Generated Baud Rates
- Timer 2 Generated Baud Rates
- Timer 3 Generated Baud Rates
- Interrupt System
- ADuC832 Hardware Design Considerations
- Other Hardware Considerations
- Development Tools
- Outline Dimensions
Data Sheet ADuC832
Rev. B | Page 63 of 92
POWER SUPPLY MONITOR
As its name suggests, the power supply monitor, once enabled,
monitors the DV
DD
supply on the ADuC832. It indicates when
any of the supply pins drop below one of four user-selectable
voltage trip points from 2.63 V to 4.37 V. For correct operation
of the power supply monitor function, AV
DD
must be equal to
or greater than 2.7 V. The monitor function is controlled via
the PSMCON SFR. If enabled via the IEIP2 SFR, the monitor
interrupts the core using the PSMI bit in the PSMCON SFR.
This bit is not cleared until the failing power supply has returned
above the trip point for at least 250 ms. This monitor function
allows the user to save working registers to avoid possible data
loss due to the low supply condition, and ensures that normal
code execution does not resume until a safe supply level has
been well established. The supply monitor is also protected
against spurious glitches triggering the interrupt circuit.
PSMCON (POWER SUPPLY MONITOR CONTROL
REGISTER )
SFR Address: DFH
Power-On Default Value: DEH
Bit Addressable : No
Table 31. PSMCON SFR Bit Designations
Bit Name Description
[7] Reserved Reserved.
[6] CMPD
DV
DD
comparator bit.
This is a read-only bit and directly reflects the state of the DV
DD
comparator.
Read 1 indicates the DV
DD
supply is above its selected trip point.
Read 0 indicates the DV
DD
supply is below its selected trip point.
[5] PSMI
Power supply monitor interrupt bit.
This bit is set high by the MicroConverter if CMPD is low, indicating low analog or digital supply. The PSMI bit can be
used to interrupt the processor. Once CMPD returns (and remains) high, a 250 ms counter is started. When this counter
times out, the PSMI interrupt is cleared. PSMI can also be written by the user. However, if either comparator output is
low, it is not possible for the user to clear PSMI.
[4:3] TPD[1:0] DV
DD
trip point selection bits. These bits select the DV
DD
trip point voltage as follows:
TPD1 TPD0 Selected DV
DD
Trip Point (V)
0 0 4.37
0 1 3.08
1 0 2.93
1 1 2.63
[2] Reserved Reserved.
[1] Reserved Reserved.
[0]
PSMEN
Power supply monitor enable bit. Set to 1 by the user to enable the power supply monitor circuit. Cleared to 0 by the
user to disable the power supply monitor circuit.