Datasheet

ADuC832 Data Sheet
Rev. B | Page 60 of 92
I
2
C-COMPATIBLE INTERFACE
The ADuC832 supports a fully licensed I
2
C serial interface. The
I
2
C interface is implemented as a full hardware slave and soft-
ware master. SDATA is the data I/O pin and SCLOCK is the
serial clock. These two pins are shared with the MOSI and
SCLOCK pins of the on-chip SPI interface. Therefore, the user
can only enable one interface or the other at any given time
(see SPE in SPICON in Tabl e 28). The uC001 Technical Note,
MicroConverter® I
2
C® Compatible Interface, describes the opera-
tion of this interface as implemented, and is available from the
MicroConverter website at www.analog.com/microconverter.
I
2
C INTERFACE SFRs
Three SFRs are used to control the I
2
C interface. These are
described in the following sections.
I2CCON (I
2
Control Register)
SFR Address: E8H
Power-On Default Value: 00H
Bit Addressable: Ye s
I2CADD (I
2
C Address Register)
SFR Address: 9BH
Power-On Default Value: 55H
Bit Addressable: No
The I2CADD SFR holds the I
2
C peripheral address for the part.
It can be overwritten by user code. Technical Note uC001 at
www.analog.com/microconverter describes the format of the
I
2
C standard 7-bit address in detail.
I2CDAT (I
2
C Data Register)
SFR Address: 9AH
Power-On Default Value: 00H
Bit Addressable: No
The I2CDAT SFR is written by the user to transmit data over
the I
2
C interface or read by user code to read data just received
by the I
2
C interface. Accessing I2CDAT automatically clears any
pending I
2
C interrupt and the I2CI bit in the I2CCON SFR. User
software should only access I2CDAT once per interrupt cycle.
Table 29. I2CCON SFR Bit Designations
Bit Name Description
[7] MDO
I
2
C software master data output bit (master mode only). This data bit is used to implement a master I
2
C transmitter interface
in software. Data written to this bit is output on the SDATA pin if the data output enable (MDE) bit is set.
[6] MDE
I
2
C software master data output enable bit (master mode only). Set by user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable SDATA pin as an input (Rx).
[5] MCO
I
2
C software master clock output bit (master mode only). This data bit is used to implement a master I
2
C transmitter interface
in software. Data written to this bit is output on the SCLOCK pin.
[4] MDI
I
2
C software master data input bit (master mode only). This data bit is used to implement a master I
2
C receiver interface in
software. Data on the SDATA pin is latched into this bit on SCLOCK if the data output enable (MDE) bit is 0.
[3] I2CM
I
2
C master/slave mode bit set by user to enable I
2
C software master mode. Cleared by user to enable I
2
C hardware slave
mode.
[2] I2CRS I
2
C reset bit (slave mode only). Set by user to reset the I
2
C interface. Cleared by user code for normal I
2
C operation.
[1] I2CTX
I
2
C direction transfer bit (slave mode only). Set by the MicroConverter if the interface is transmitting. Cleared by the
MicroConverter if the interface is receiving.
[0] I2CI
I
2
C interrupt bit (slave mode only). Set by the MicroConverter after a byte has been transmitted or received. Cleared
automatically when user code reads the I2CDAT SFR (see the I2CADD (I2C Address Register) section).