Datasheet

Data Sheet ADuC832
Rev. B | Page 55 of 92
PULSE-WIDTH MODULATOR (PWM)
The PWM on the ADuC832 is a highly flexible PWM offering
programmable resolution and an input clock, and can be confi-
gured for any one of six different modes of operation. Two of
these modes allow the PWM to be configured as a Σ-Δ DAC
with up to 16 bits of resolution. A block diagram of the PWM
is shown in Figure 56.
CLOCK
SELECT
PROGRAMMABLE
DIVIDER
COMPARE
MODE PWM0H/L
f
VCO
T0/EXTERNAL PWM CLOCK
f
XTAL
/15
f
XTAL
P2.6
P2.7
16-BIT PWM COUNTER
PWM1H/L
02987-045
Figure 56. PWM Block Diagram
The PWM uses five SFRs: the control SFR (PWMCON) and
four data SFRs (PWM0H, PWM0L, PWM1H, and PWM1L).
PWMCON (as described in Table 27) controls the different
modes of operation of the PWM as well as the PWM clock
frequency. PWM0H/PWM0L and PWM1H/PWM1L are the data
registers that determine the duty cycles of the PWM outputs. The
output pins that the PWM uses are determined by the CFG832
register, and can be either P2.6 and P2.7 or P3.4 and P3.3. In
this section of the data sheet, it is assumed that P2.6 and P2.7
are selected as the PWM outputs.
To use the PWM user software, first write to PWMCON to
select the PWM mode of operation and the PWM input clock.
Writing to PWMCON also resets the PWM counter. In any of
the 16-bit modes of operation (Mode 1, Mode 3, Mode 4, and
Mode 6), user software should write to the PWM0L or PWM1L
SFR first. This value is written to a hidden SFR. Writing to the
PWM0H or PWM1H SFRs updates both the PWMxH and the
PWMxL SFRs but does not change the outputs until the end of
the PWM cycle in progress. The values written to these 16-bit
registers are then used in the next PWM cycle.
PWMCON (PWM CONTROL SFR)
SFR Address: AEH
Power-On Default Value: 00H
Bit Addressable: No
Table 27. PWMCON SFR Bit Designations
Bit Name Description
[7]
SNGL
Turns off PWM output at P2.6 or P3.4, leaving port pin free for digital I/O.
[6:4] MD[2:0] PWM mode bits. The MD[2:0] bits choose the PWM mode as follows:
MD2 MD1 MD0 Mode
0 0 0 Mode 0: PWM disabled
0 0 1 Mode 1: single variable resolution PWM on P2.7 or P3.3
0 1 0 Mode 2: twin 8-bit PWM
0 1 1 Mode 3: twin 16-bit PWM
1 0 0 Mode 4: dual NRZ 16-bit Σ-Δ DAC
1
0
1
Mode 5: dual 8-bit PWM
1 1 0 Mode 6: dual RZ 16-bit Σ-Δ DAC
1 1 1 Reserved for future use
[3:2] CDIV[1:0] PWM clock divider. These bits scale the clock source for the PWM counter as follows:
CDIV1 CDIV0 PWM Counter
0 0 Selected clock/1
0
1
Selected clock/4
1 0 Selected clock/16
1 1 Selected clock/64
[1:0]
CSEL[1:0]
PWM clock divider. These bits select the clock source for the PWM as follows:
CSEL1 CSEL0 PWM Clock
0 0 f
XTAL
/15
0 1 f
XTAL
1 0 External input at P3.4/T0
1 1 f
VCO
= 16.78 MHz