Datasheet

Data Sheet ADuC832
Rev. B | Page 53 of 92
SOURCE/SINK CURRENT (mA)
4
0 5 10 15
OUTPUT VOLTAGE (V)
3
1
0
DAC LOADED WITH 0000H
DAC LOADED WITH 0FFFH
02987-043
Figure 54. Source and Sink Current Capability with V
REF
= AV
DD
= 3 V
To reduce the effects of the saturation of the output amplifier at
values close to ground and to give reduced offset and gain errors,
the internal buffer can be bypassed. This is done by setting the
DBUF bit in the CFG832 register. This allows a full rail-to-rail
output from the DAC, which should then be buffered externally
using a dual-supply op amp to obtain a rail-to-rail output. This
external buffer should be located as near as physically possible
to the DAC output pin on the PCB. Note that the unbuffered
mode only works in the 0 V to V
REF
range.
To drive significant loads with the DAC outputs, external
buffering may be required (even with the internal buffer
enabled), as illustrated in Figure 55. A list of recommended op
amps is shown in Table 20.
ADuC832
DAC0
DAC1
0
2987-044
Figure 55. Buffering the DAC Outputs
The DAC output buffer also features a high impedance disable
function. In the chip’s default power-on state, both DACs are
disabled, and their outputs are in a high impedance state (or
three-state) where they remain inactive until enabled in
software. This means that if a zero output is desired during
power-up or power-down transient conditions, then a pull-
down resistor must be added to each DAC output. Assuming
this resistor is in place, the DAC outputs remain at ground
potential whenever the DAC is disabled.