Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Explanation of Typical Performance Plots
- Memory Organization
- Special Function Registers (SFRs)
- Special Function Registers
- ADC Circuit Information
- Calibrating the ADC
- Initiating Calibration in Code
- Nonvolatile Flash/EE Memory
- Using the Flash/EE Data Memory
- User Interface to Other On-Chip ADuC832 Peripherals
- On-Chip PLL
- Pulse-Width Modulator (PWM)
- PWM Modes of Operation
- Serial Peripheral Interface
- I2C-Compatible Interface
- Dual Data Pointers
- Power Supply Monitor
- Watchdog Timer
- Time Interval Counter (TIC)
- 8052-Compatible On-Chip Peripherals
- Timer/Counter 0 And Timer/Counter 1 Operating Modes
- Timer/Counter 2
- UART Serial Interface
- SBUF
- SCON (UART Serial Port Control Register)
- Mode 0: 8-Bit Shift Register Mode
- Mode 1: 8-Bit UART, Variable Baud Rate
- Mode 2: 9-Bit UART with Fixed Baud Rate
- Mode 3: 9-Bit UART with Variable Baud Rate
- UART Serial Port Baud Rate Generation
- Timer 1 Generated Baud Rates
- Timer 2 Generated Baud Rates
- Timer 3 Generated Baud Rates
- Interrupt System
- ADuC832 Hardware Design Considerations
- Other Hardware Considerations
- Development Tools
- Outline Dimensions

Data Sheet ADuC832
Rev. B | Page 43 of 92
CALIBRATING THE ADC
There are two hardware calibration modes provided that can be
easily initiated by user software. The ADCCON3 SFR is used to
calibrate the ADC. The typical bit (ADCCON3[1]) and the CS3
to CS0 bits (ADCCON2[3:0]) set up the calibration modes.
Device calibration can be initiated to compensate for significant
changes in operating conditions frequency, analog input range,
reference voltage, and supply voltages. In this calibration mode,
offset calibration uses the internal AGND selected via ADCCON2
register bits CS[3:0] = 1011, and gain calibration uses the internal
V
REF
selected by CS[3:0] = 1100. Offset calibration should be
executed first, followed by gain calibration.
System calibration can be initiated to compensate for both internal
and external system errors. To perform system calibration using
an external reference, tie system ground and reference to any
two of the six selectable inputs. Enable external reference mode
(ADCCON1[6]). Select the channel connected to AGND via
CS[3:0] and perform system offset calibration. Select the channel
connected to V
REF
via CS[3:0] and perform system gain calibration.
The ADC should be configured to use settings for an ADCCLK
of divide-by-16 and divide-by-4 acquisition clocks.