Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Explanation of Typical Performance Plots
- Memory Organization
- Special Function Registers (SFRs)
- Special Function Registers
- ADC Circuit Information
- Calibrating the ADC
- Initiating Calibration in Code
- Nonvolatile Flash/EE Memory
- Using the Flash/EE Data Memory
- User Interface to Other On-Chip ADuC832 Peripherals
- On-Chip PLL
- Pulse-Width Modulator (PWM)
- PWM Modes of Operation
- Serial Peripheral Interface
- I2C-Compatible Interface
- Dual Data Pointers
- Power Supply Monitor
- Watchdog Timer
- Time Interval Counter (TIC)
- 8052-Compatible On-Chip Peripherals
- Timer/Counter 0 And Timer/Counter 1 Operating Modes
- Timer/Counter 2
- UART Serial Interface
- SBUF
- SCON (UART Serial Port Control Register)
- Mode 0: 8-Bit Shift Register Mode
- Mode 1: 8-Bit UART, Variable Baud Rate
- Mode 2: 9-Bit UART with Fixed Baud Rate
- Mode 3: 9-Bit UART with Variable Baud Rate
- UART Serial Port Baud Rate Generation
- Timer 1 Generated Baud Rates
- Timer 2 Generated Baud Rates
- Timer 3 Generated Baud Rates
- Interrupt System
- ADuC832 Hardware Design Considerations
- Other Hardware Considerations
- Development Tools
- Outline Dimensions

ADuC832 Data Sheet
Rev. B | Page 4 of 92
REVISION HISTORY
4/13—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 89
Changes to Ordering Guide .......................................................... 89
9/09—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changed 16.77 MHz to 16.78 MHz Throughout ......................... 1
Changes to Reference Input/Output, Output Voltage Parameter,
Endnote 19, and Endnote 20, Table 1 ............................................ 9
Moved Timing Specifications Section ......................................... 10
Changes to Figure 3 ........................................................................ 10
Changes to Table 3 .......................................................................... 11
Changes to Table 4 .......................................................................... 12
Changes to Table 5 .......................................................................... 13
Changes to Table 11 ........................................................................ 19
Changes to Figure 15 and Table 13 ............................................... 21
Changes to Figure 16, Figure 17, Figure 20, and Figure 21 ....... 26
Added Explanation of Typical Performance Plots Section ....... 30
Changes to Flash/EE Program Memory, Flash/EE Data
Memory, and General-Purpose RAM Sections .......................... 31
Changes to Figure 36 ...................................................................... 34
Changes to Figure 39 and Figure 40 ............................................. 39
Changes to Table 20 ........................................................................ 40
Changes to A Typical DMA Mode Configuration Example
Section .............................................................................................. 41
Changed 16.777216 MHz to 16.78 MHz Throughout .............. 41
Changes to Table 21 ....................................................................... 48
Changes to Using the DAC Section and Figure 52 .................... 52
Changes to Figure 54 Caption ...................................................... 53
Changes to Figure 56 ...................................................................... 55
Changed 16.77 MHz to 16.78 MHz ............................................. 56
Changes to Figure 60 ...................................................................... 57
Changes to Table 31 ....................................................................... 63
Deleted Figure 65 and Figure 66; Renumbered Sequentially ... 66
Deleted ASPIRE—IDE Section..................................................... 66
Deleted Figure 67 ............................................................................ 67
Changes to Table 34 ....................................................................... 67
Changes to Figure 68, Figure 69, Figure 70, and Table 35 ........ 68
Changes to Figure 84 ...................................................................... 78
Changes to External Memory Interface Section ........................ 82
Changes to Power Supplies Section ............................................. 83
Changes to Table 50 ....................................................................... 84
Changes to Figure 94 ...................................................................... 86
Changes to Single-Pi
n Emulation Mode Section ....................... 87
Changes to QuickStart Development System Section and
QuickStart Plus Development System Section ........................... 88
Updated Outline Dimensions ....................................................... 89
Changes to Ordering Guide .......................................................... 89
11/02—Revision 0: Initial Version