Datasheet

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Table Of Contents

Features
Applications
Functional Block Diagram
General Description
Revision History
Specifications
- Timing Specifications
Absolute Maximum Ratings
- ESD Caution
Pin Configurations and Function Descriptions
Typical Performance Characteristics
Terminology
- ADC Specifications
- DAC Specifications
Explanation of Typical Performance Plots
Memory Organization
- Flash/EE Program Memory
- Flash/EE Data Memory
- General-Purpose RAM
- External Data Memory (External XRAM)
- Internal XRAM
Special Function Registers (SFRs)
- Accumulator SFR (ACC)
- B SFR (B)
- Stack Pointer (SP and SPH)
- Data Pointer (DPTR)
- Program Status Word (PSW)
- Power Control SFR (PCON)
Special Function Registers
ADC Circuit Information
- General Overview
- ADC Transfer Function
- Typical Operation
- Driving the Analog-to-Digital Converter
- Voltage Reference Connections
- Configuring the ADC
- ADC DMA Mode
  - A Typical DMA Mode Configuration Example
- Micro-Operation During ADC DMA Mode
- ADC Offset and Gain Calibration Coefficients
Calibrating the ADC
Initiating Calibration in Code
Nonvolatile Flash/EE Memory
- Flash/EE Memory Overview
- Flash/EE Memory and the ADuC832
- ADuC832 Flash/EE Memory Reliability
- Using the Flash/EE Program Memory
- Flash/EE Program Memory Security
Using the Flash/EE Data Memory
- ECON—Flash/EE Memory Control SFR
- Example: Programming the Flash/EE Data Memory
- Flash/EE Memory Timing
- ADuC832 Configuration SFR (CFG832)
  - CFG832 (ADuC832 Configuration SFR)
User Interface to Other On-Chip ADuC832 Peripherals
- DAC
  - DACCON (DAC Control Register)
  - DACxH/DACxL (DAC Data Registers)
- Using the DAC
On-Chip PLL
- PLLCON (PLL Control Register)
Pulse-Width Modulator (PWM)
- PWMCON (PWM Control SFR)
PWM Modes of Operation
- Mode 0: PWM Disabled
- Mode 1: Single Variable Resolution PWM
- Mode 2: Twin 8-Bit PWM
- Mode 3: Twin 16-Bit PWM
- Mode 4: Dual NRZ 16-Bit Σ-Δ DAC
- Mode 5: Dual 8-Bit PWM
- Mode 6: Dual RZ 16-Bit Σ-Δ DAC
Serial Peripheral Interface
- MISO (Master Input, Slave Output Data Pin)
- MOSI (Master Output, Slave Input Pin)
- SCLOCK (Serial Clock I/O Pin)
- (Slave Select Input Pin)
  - SPICON (SPI Control Register)
  - SPIDAT (SPI Data Register)
- Using the SPI Interface
- SPI Interface—Master Mode
- SPI Interface—Slave Mode
I2C-Compatible Interface
- I2C Interface SFRs
- Overview
- Software Master Mode
- Hardware Slave Mode
Dual Data Pointers
- DPCON (Data Pointer Control SFR)
  - Notes
Power Supply Monitor
- PSMCON (Power Supply Monitor Control Register )
Watchdog Timer
- Example Write Instruction
Time Interval Counter (TIC)
- TIMECON (TIC Control Register)
- INTVAL (User Time Interval Select Register)
- HTHSEC (Hundredths Seconds Time Register)
- SEC (Seconds Time Register)
- MIN (Minutes Time Register)
- HOUR (Hours Time Register)
8052-Compatible On-Chip Peripherals
- Parallel I/O
- Port 0
- Port 1
- Port 2
- Port 3
- Additional Digital I/O
- Read-Modify-Write Instructions
- Timers/Counters
  - TMOD (Timer/Counter 0 and Timer/Counter 1 Mode Register)
  - TCON (Timer/Counter 0 and Timer/Counter 1 Control Register)
- Timer/Counter 0 and Timer/Counter 1 Data Registers
  - TH0 and TL0
  - TH1 and TL1
Timer/Counter 0 And Timer/Counter 1 Operating Modes
- Mode 0 (13-Bit Timer/Counter)
- Mode 1 (16-Bit Timer/Counter)
- Mode 2 (8-Bit Timer/Counter with Autoreload)
- Mode 3 (Two 8-Bit Timer/Counters)
Timer/Counter 2
- T2CON (Timer/Counter 2 Control Register)
- Timer/Counter 2 Data Registers
  - TH2 and TL2
  - RCAP2H and RCAP2L
- Timer/Counter Operation Modes
  - 16-Bit Autoreload Mode
  - 16-Bit Capture Mode
UART Serial Interface
- SBUF
- SCON (UART Serial Port Control Register)
- Mode 0: 8-Bit Shift Register Mode
- Mode 1: 8-Bit UART, Variable Baud Rate
- Mode 2: 9-Bit UART with Fixed Baud Rate
- Mode 3: 9-Bit UART with Variable Baud Rate
- UART Serial Port Baud Rate Generation
- Timer 1 Generated Baud Rates
- Timer 2 Generated Baud Rates
- Timer 3 Generated Baud Rates
Interrupt System
- IE (Interrupt Enable Register)
- IP (Interrupt Priority Register )
- IEIP2 (Secondary Interrupt Enable Register)
- Interrupt Priority
- Interrupt Vectors
ADuC832 Hardware Design Considerations
- Clock Oscillator
- External Memory Interface
- Power Supplies
- Power Consumption
- Power Saving Modes
- Power-On Reset
- Grounding and Board Layout Recommendations
Other Hardware Considerations
- In-Circuit Serial Download Access
- Embedded Serial Port Debugger
- Single-Pin Emulation Mode
- Typical System Configuration
Development Tools
- QuickStart Development System
  - Download—In-Circuit Serial Downloader
- QuickStart Plus Development System
Outline Dimensions
- Ordering Guide

ADuC832 Data Sheet

Rev. B | Page 38 of 92

ADCCON3 (ADC Control SFR 3)

SFR Address: F5H

SFR Power-On Default Value: 00H

Bit Addressable: No

The ADCCON3 register controls the operation of various

calibration modes as well as giving an indication of ADC busy

status.

Table 18. ADCCON3 SFR Bit Designations

Bit Name Description

[7] Busy

The ADC busy status bit is a read-only status bit that is set during a valid ADC conversion or calibration cycle. Busy is

automatically cleared by the core at the end of conversion or calibration.

[6] GNCLD Gain calibration disable bit. Set to 0 to enable gain calibration. Set to 1 to disable gain calibration.

[5:4] AVGS[1:0] Number of averages selection bits. These bits select the number of ADC readings averaged during a calibration cycle.

AVGS1 AVGS0 Number of Averages

0 0 15

0 1 1

1 0 31

1 1 63

[3] RSVD Reserved. This bit should always be written as 0.

[2] RSVD This bit should always be written as 1 by the user when performing calibration.

[1] Typical Calibration type select bit. This bit selects between offset (zero-scale) and gain (full-scale) calibration.

Set to 0 for offset calibration.

Set to 1 for gain calibration.

[0] SCAL

Start calibration cycle bit. When set, this bit starts the selected calibration cycle. It is automatically cleared when the

calibration cycle is completed.