Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Explanation of Typical Performance Plots
- Memory Organization
- Special Function Registers (SFRs)
- Special Function Registers
- ADC Circuit Information
- Calibrating the ADC
- Initiating Calibration in Code
- Nonvolatile Flash/EE Memory
- Using the Flash/EE Data Memory
- User Interface to Other On-Chip ADuC832 Peripherals
- On-Chip PLL
- Pulse-Width Modulator (PWM)
- PWM Modes of Operation
- Serial Peripheral Interface
- I2C-Compatible Interface
- Dual Data Pointers
- Power Supply Monitor
- Watchdog Timer
- Time Interval Counter (TIC)
- 8052-Compatible On-Chip Peripherals
- Timer/Counter 0 And Timer/Counter 1 Operating Modes
- Timer/Counter 2
- UART Serial Interface
- SBUF
- SCON (UART Serial Port Control Register)
- Mode 0: 8-Bit Shift Register Mode
- Mode 1: 8-Bit UART, Variable Baud Rate
- Mode 2: 9-Bit UART with Fixed Baud Rate
- Mode 3: 9-Bit UART with Variable Baud Rate
- UART Serial Port Baud Rate Generation
- Timer 1 Generated Baud Rates
- Timer 2 Generated Baud Rates
- Timer 3 Generated Baud Rates
- Interrupt System
- ADuC832 Hardware Design Considerations
- Other Hardware Considerations
- Development Tools
- Outline Dimensions
ADuC832 Data Sheet
Rev. B | Page 34 of 92
SPECIAL FUNCTION REGISTERS
All registers except the program counter and the four general-
purpose register banks reside in the special function register
(SFR) area. The SFR registers include control, configuration,
and data registers that provide an interface between the CPU
and other on-chip peripherals.
Figure 36 shows a full SFR memory map and SFR contents on
reset. Unoccupied SFR locations are shown dark-shaded in
Figure 36 (labeled not used). Unoccupied locations in the SFR
address space are not implemented, that is, no register exists at
that location. If an unoccupied location is read, an unspecified
value is returned. SFR locations reserved for on-chip testing are
shown lighter shaded in Figure 36 (labeled reserved) and should
not be accessed by user software. Sixteen of the SFR locations
are also bit addressable and denoted by Footnote 1 in Figure 36,
that is, the bit addressable SFRs are those whose address ends in
0H or 8H.
SPICON
1
F8H
04H
F0H
00H
00H
DAC0L
F9H
DAC0H DAC1L DAC1H DACCON
FDH 04HFCH 00H
F3H 00HF2H 20H
FAH 00H00H
F1H
00H
FBH 00H
RESERVED
B
1
ADCOFSL
3
ADCOFSH
3
ADCGAINL
3
ADCGAINH
3
ADCCON3
F5H
RESERVED
I2CCON
1
E8H
RESERVED
ACC
1
E0H
RESERVED
ADCCON2
1
D8H
ADCDATAL ADCDATAH
DAH 00H
RESERVED
PSW
1
D0H
DMAL DMAH
D2H
DMAP
00H D3H 00H D4H
00H
RESERVED
T2CON
1
C8H 00H
RCAP2L
CAH 00H
RCAP2H
CBH
TL2
CCH
TH2
CDH
RESERVED
WDCON
1
C0H
IP
1
B8H 00H B9H 00H
ECON EDATA1 EDATA2
BDH
IE
1
IEIP2
P2
1
SCON
1
SBUF I2CDAT
NOT USED
P1
1, 2
NOT USED
TCON
1
TMOD TL0 TL1 TH0 TH1
P0
1
80H
SP DPL DPH DPP
84H 00H 87H 00H83H 00H82H 00H81H 07H
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
RESERVEDRESERVEDRESERVED
RESERVEDRESERVED
RESERVED
RESERVEDRESERVEDRESERVED
NOT USED
NOT USEDNOT USED
P3
1
B0H
NOT USEDNOT USEDNOT USEDNOT USEDNOT USED
SPIDAT
F7H 00H
ADCCON1
EFH
RESERVED
PSMCON
DFH DEH
EADRL
EDATA3 EDATA4
NOT USED
PCON
IE0
89H 0
IT0
88H 0
TCON
88H 00H
MNEMONIC
SFR ADDRESS
DEFAULT VALUE
MNEMONIC
DEFAULT VALUE
SFR ADDRESS
THESE BITS ARE CONTAINED IN THIS BYTE.
SFR MAP KEY:
1
SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.
2
THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT; THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE
PORT PINS, WRITE A 0 TO THE CORRESPONDING PORT 1 SFR BIT.
3
CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.
RESERVEDRESERVED
RESERVED
TIMECON HTHSEC SEC MIN HOUR DPCON
PWMCON
AEH 00H
CFG832
RESERVEDRESERVED
RESERVEDRESERVEDRESERVEDRESERVED
RESERVEDRESERVED
T3FD
00H 00H
PWM0L PWM0H PWM1L
SPH
00H
00H
00H 00H
00H
B1H
B2H
B4H
B7H
00HC7H
00HC6H
00HBFH00HBEH
RESERVED
CHIPID
C2H 2XH
EADRH
RESERVED
PLLCON
D7H
I2CADD
ISPI
FFH
0
WCOL
FEH
0
SPE
FDH
0
SPIM
FCH
0
CPOL
FBH
0
CPHA
FAH
SPR1
F9H
0
SPR0
F8H
0
BITS
1
MDO
EFH
0
EEH
0
MCO
EDH
0
ECH
0
EBH
0
EAH
E9H
0
E8H
0
BITS
E7H
0
E6H
0
E5H
0
E4H
0
E3H
0
E2H E1H
0
E0H
0
BITS
ADCI
DFH
0
DMA
DEH
0
CCONV
DDH
0
SCONV
DCH
0
CS3
DBH
0
CS2
DAH
CS1
D9H
0
CS0
D8H
0
BITS
CY
D7H
0
AC
D6H
0
F0
D5H
0
RS1
D4H
0
RS0
D3H
0
OV
D2H
F1
D1H
0
P
D0H
0
BITS
TF2
CFH 0
EXF2
CEH 0
RCLK
CDH 0
TCLK
CCH 0
EXEN2
CBH 0
TR2
CAH
CNT2
C9H 0
CAP2
C8H 0
BITS
PRE3
C7H 0
PRE2
C6H 0
PRE1
C5H 0 C4H 1
WDIR
C3H 0
WDS
C2H
WDE
C1H 0
WDWR
C0H 0
BITS
BFH 0
PADC
BEH 0
PT2
BDH 0
PS
BCH 0
PT1
BBH 0
PX1
BAH
PT0
B9H 0
PX0
B8H 0
BITS
RD
B7H
1
WR
B6H
1
T1
B5H
1
T0
B4H
1
INT1
B3H
1
INT0
B2H
TxD
B1H
1
RxD
B0H
1
BITS
EA
AFH
EADC
AEH
ET2
ADH
ES
ACH
ET1
ABH
EX1
AAH
ET0
A9H
EX0
A8H 00
BITS
A7H A6H A5H 111 A4H 1 A3H 1 A2H A1H 1 A0H 1
BITS
SM0
9FH 0
SM1
9EH 0
SM2
9DH 0
REN
9CH 0
TB8
9BH 0
RB8
9AH
TI
99H 0
RI
98H 0
BITS
97H 1 96H 1 95H 1 94H 1 93H 1 92H
T2EX
91H 1
T2
90H 1
BITS
TF1
8FH 0
TR1
8EH 0
TF0
8DH 0
TR0
8CH 0
IE1
8BH 0
IT1
8AH
IE0
89H 0
IT0
88H 0
BITS
87H 1 86H 1 85H 1 84H 1 83H 1 82H 81H 1 80H 1
BITS
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0 0
I2CMMDE
PRE0
MDI
I2CTX
I2CI
F7H
0
F6H
0
F5H
0
F4H
0
F3H
0
F2H
F1H
0
F0H
0
BITS
0
I2CRS
T3CON
INTVAL
PWM1H
53H
00H 00H 00H
B3H
FFH
90H FFH
88H 8CH 00H 8DH
9DH 9EH
00H8BH 00H8AH 00H89H 00H00H
A0H A4H 00H A5H 00H A6H 00H A7H 00H
AFH 00H
A3H 00HA2H 00HA1H 00HFFH
98H 9BH 55H9AH 00H99H 00H00H
FFH
A8H A0HA9H00H
00HBCH 00H
10H
00H
00H D9H 00H
00H
00H
00HF4H 00H
02987-025
Figure 36. Special Function Register Locations and Reset Values