Datasheet

Data Sheet ADuC832
Rev. B | Page 23 of 92
Pin No.
Mnemonic MQFP LFCSP Type Description
P3.4/T0/PWMC/PWM0/EXTCLK 22 24 I/O Input/Output Port 3 (P3.4). Port 3 is a bidirectional port with internal pull-up resistors.
Port 3 pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled
externally low sources current because of the internal pull-up resistors.
I
Timer/Counter 0 Input (T0).
I PWM Clock Input (PWMC).
O PWM0 Voltage Output (PWM0). PWM outputs can be configured to uses
Port 2.6 and Port 2.7, or Port 3.4 and Port 3.3.
I Input for External Clock Signal (EXTCLK). This pin must be enabled via the CFG832
register.
P3.5/T1/
CONVST
23 25 I/O Input/Output Port 3 (P3.5). Port 3 is a bidirectional port with internal pull-up resistors.
Port 3 pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled
externally low sources current because of the internal pull-up resistors.
I Timer/Counter 1 Input (T1).
I Active Low Convert Start Logic Input for the ADC Block When the External Convert
Start Function is Enabled (
CONVST
). A low-to-high transition on this input puts the
track-and-hold into its hold mode and starts conversion.
P3.6/
WR
24
26
I/O
Input/Output Port 3 (P3.6). Port 3 is a bidirectional port with internal pull-up resistors.
Port 3 pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled
externally low sources current because of the internal pull-up resistors.
O
Write Control Signal, Logic Output (
WR
). Latches the data byte from Port 0 into the
external data memory.
P3.7/
RD
25 27 O Input/Output Port 3 (P3.7). Port 3 is a bidirectional port with internal pull-up resistors.
Port 3 pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled
externally low sources current because of the internal pull-up resistors.
O
Read Control Signal, Logic Output (
RD
). Enables the external data memory to Port 0.
SCLOCK 26 28 I/O Serial Clock Pin for I
2
C-Compatible or SPI Serial Interface Clock.
SDATA/MOSI 27 29 I/O User Selectable, I
2
C-Compatible or SPI Data Input/Output Pin (SDATA).
I/O SPI Master Output/Slave Input Data I/O Pin for SPI Interface (MOSI).
P2.0/A8/A16 28 30 I/O Input/Output Port 2 (P2.0). Port 2 is a bidirectional port with internal pull-up resistors.
Port 2 pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low sources current because of the internal pull-up resistors.
I/O
External Memory Addresses (A8/A16). Port 2 emits the high order address bytes
during fetches from external program memory and middle and high order address
bytes during accesses to the external 24-bit external data memory space.
P2.1/A9/A17 29 31 I/O Input/Output Port 2 (P2.1). Port 2 is a bidirectional port with internal pull-up resistors.
Port 2 pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low sources current because of the internal pull-up resistors.
I/O External Memory Addresses (A9/A17). Port 2 emits the high order address bytes
during fetches from external program memory and middle and high order address
bytes during accesses to the external 24-bit external data memory space.
P2.2/A10/A18 30 32 I/O Input/Output Port 2 (P2.2). Port 2 is a bidirectional port with internal pull-up resistors.
Port 2 pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low sources current because of the internal pull-up resistors.
I/O External Memory Addresses (A10/A18). Port 2 emits the high order address bytes
during fetches from external program memory and middle and high order address
bytes during accesses to the external 24-bit external data memory space.
P2.3/A11/A19 31 33 I/O Input/Output Port 2 (P2.3). Port 2 is a bidirectional port with internal pull-up resistors.
Port 2 pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low sources current because of the internal pull-up resistors.
I/O External Memory Addresses (A11/A19). Port 2 emits the high order address bytes
during fetches from external program memory and middle and high order address
bytes during accesses to the external 24-bit external data memory space.
XTAL1 32 34 I Input to the Inverting Oscillator Amplifier.