Datasheet

Data Sheet ADuC832
Rev. B | Page 17 of 92
Table 9. SPI Master Mode Timing (CPHA = 0)
Parameter
1
Description Min Typ Max Unit
t
SL
SCLOCK low pulse width
2
476 ns
t
SH
SCLOCK high pulse width
2
476 ns
t
DAV
Data output valid after SCLOCK edge 50 ns
t
DOSU
Data output setup before SCLOCK edge 150 ns
t
DSU
Data input setup time before SCLOCK edge
100
ns
t
DHD
Data input hold time after SCLOCK edge 100 ns
t
DF
Data output fall time 10 25 ns
t
DR
Data output rise time 10 25 ns
t
SR
SCLOCK rise time 10 25 ns
t
SF
SCLOCK fall time
10
25
ns
1
See Figure 11.
2
Characterized under the following conditions:
a. Core clock divider bits (CD2, CD1, and CD0 bits in PLLCON SFR) set to 0, 1, and 1, respectively, that is, core clock frequency = 2.09 MHz
b. SPI bit rate selection bits (SPR1 and SPR0 bits in SPICON SFR) set to 0 and 0, respectively.
t
DAV
t
SH
t
SL
t
SR
t
SF
t
DOSU
t
DF
t
DR
t
DSU
t
DHD
MSB
BIT 6 TO 1
LSB
BIT 6 TO 1
LSB IN
MSB IN
02987-094
MISO (O)
MOSI (I)
SCLOCK (O)
(CPOL = 1)
SCLOCK (O)
(CPOL = 0)
Figure 11. SPI Master Mode Timing (CPHA = 0)