Datasheet

Data Sheet ADuC832
Rev. B | Page 15 of 92
Table 7. I
2
C-Compatible Interface Timing
Parameter
1
Description Min Max Unit
t
L
SCLOCK low pulse width 4.7 μs
t
H
SCLOCK high pulse width 4.0 μs
t
SHD
Start condition hold time 0.6 μs
t
DSU
Data setup time 100 μs
t
DHD
Data hold time
0.9
μs
t
RSU
Setup time for repeated start 0.6 μs
t
PSU
Stop condition setup time 0.6 μs
t
BUF
Bus free time between a stop condition and a start condition 1.3 μs
t
R
Rise time of both SCLOCK and SDATA 300 ns
t
F
Fall time of both SCLOCK and SDATA
300
ns
t
SUP
2
Pulse width of spike suppressed 50 ns
1
See Figure 9.
2
Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns.
SDATA (I/O)
STOP
CONDITION
MSBACK
SCLOCK (I)
t
PSU
t
SHD
t
DSU
t
DHD
t
SUP
t
H
t
DSU
t
DHD
t
RSU
t
F
t
R
t
F
t
R
t
L
t
BUF
START
CONDITION
t
SUP
LSB
MSB
1
2–7
8
PS
9
S(R)
REPEATED
START
1
02987-092
Figure 9. I
2
C Compatible Interface Timing