Datasheet

ADuC832 Data Sheet
Rev. B | Page 14 of 92
Table 6. UART Timing (Shift Register Mode)
Parameter
1
Description
16.78 MHz Core_CLK Variable Clock
Min Typ Max Min Typ Max Unit
t
XLXL
Serial port clock cycle time 715 12t
CK
μs
t
QVXH
Output data setup to clock 463 10t
CK
− 133 ns
t
DVXH
Input data setup to clock
252
2t
CK
+ 133
ns
t
XHDX
Input data hold after clock 0 0 ns
t
XHQX
Output data hold after clock 22 2t
CK
− 117 ns
1
See Figure 8.
ALE (O)
TxD
(OUTPUT CLOCK)
RxD
(OUTPUT DATA)
RxD
(INPUT DATA)
t
XLXL
t
QVXH
t
XHQX
t
DVXH
t
XHDX
SET RI
OR
SET TI
0
6
BIT 1BIT 6
BIT 6
MSB
MSB
BIT 1
7
LSB
LSB
1
02987-091
Figure 8. UART Timing in Shift Register Mode