Datasheet

Data Sheet ADuC832
Rev. B | Page 13 of 92
Table 5. External Data Memory Write Cycle
Parameter
1
Description
16.78 MHz Core_CLK Variable Clock
Min Max Min Max Unit
t
WLWH
WR pulse width
257 6t
CK
− 100 ns
t
AVLL
Address valid before ALE low 19 t
CK
− 40 ns
t
LLAX
Address hold after ALE low
24
t
CK
− 35
ns
t
LLWL
ALE low to
WR low
128 228 3t
CK
− 50 3t
CK
+50 ns
t
AVWL
Address valid to
WR Low
108 4t
CK
− 130 ns
t
QVWX
Data valid to
WR transition
9 t
CK
− 50 ns
t
QVWH
Data setup before
WR
267 7t
CK
− 150 ns
t
WHQX
Data and address hold after
WR
9 t
CK
− 50 ns
t
WHLH
WR high to ALE high
19 257 t
CK
− 40 6t
CK
− 100 ns
1
See Figure 7.
M
CLK
ALE (O)
PORT 2 (O)
t
WHLH
t
WLWH
t
LLWL
t
AVWL
t
LLAX
t
AVLL
t
QVWX
t
QVWH
t
WHQX
DATA
PSEN (O)
WR (O)
A16 TO A23
A0 TO A7
A8 TO A15
02987-090
Figure 7. External Data Memory Write Cycle