Datasheet

ADuC832 Data Sheet
Rev. B | Page 12 of 92
Table 4. External Data Memory Read Cycle
16.78 MHz Core_CLK Variable Clock
Parameter
1
Description Min Max Min Max Unit
t
RLRH
RD
pulse width
257 6t
CK
− 100 ns
t
AVLL
Address valid before ALE low 19 t
CK
− 40 ns
t
LLAX
Address hold after ALE low 24 t
CK
− 35 ns
t
RLDV
RD
low to valid data in
133 5t
CK
− 165 ns
t
RHDX
Data and address hold after RD
0 0 ns
t
RHDZ
Data float after RD
49 2t
CK
− 70 ns
t
LLDV
ALE low to valid data in 326 8t
CK
− 150 ns
t
AVDV
Address to valid data in 371 9t
CK
− 165 ns
t
LLWL
ALE low to RD
low
128 228 3t
CK
− 50 3t
CK
+50 ns
t
AVWL
Address valid to RD
low
108 4t
CK
− 130 ns
t
RLAZ
RD
low to address float
0 0 ns
t
WHLH
RD
high to ALE high
19 257 t
CK
− 40 6t
CK
− 100 ns
1
See Figure 6.
M
CLK
ALE (O)
PORT 0 (I/O)
PORT 2 (O)
t
WHLH
t
LLDV
t
LLWL
t
RLRH
t
AVWL
t
LLAX
t
AVLL
t
RLAZ
t
RHDX
t
RHDZ
t
AVDV
D0 TO D7 (IN)A0 TO A7 (OUT)
A8 TO A15A16 TO A23
t
RLDV
PSEN (O)
RD (O)
02987-089
Figure 6. External Data Memory Read Cycle