Datasheet

Data Sheet ADuC832
Rev. B | Page 11 of 92
Table 3. External Program Memory Read Cycle
Parameter
1
Description
16.78 MHz Core_CLK Variable Clock
Min Max Min Max Unit
t
LHLL
ALE pulse width 79 2t
CK
− 40 ns
t
AVLL
Address valid to ALE low 19 t
CK
− 40 ns
t
LLAX
Address hold after ALE low 29 t
CK
− 30 ns
t
LLIV
ALE low to valid instruction in 138 4t
CK
− 100 ns
t
LLPL
ALE low to PSEN
low
29 t
CK
− 30 ns
t
PLPH
PSEN
pulse width
133 3t
CK
− 45 ns
t
PLIV
PSEN
low to valid instruction in
73 3t
CK
− 105 ns
t
PXIX
Instruction in, hold after PSEN
0 0 ns
t
PXIZ
Instruction in, float after PSEN
34 t
CK
− 25 ns
t
AVIV
Address to valid instruction in 193 5t
CK
− 105 ns
t
PLAZ
PSEN
low to address float
25 25 ns
t
PHAX
Address hold after PSEN
high
0 0 ns
1
See Figure 5.
M
CLK
ALE (O)
PSEN (O)
PORT 0 (I/O)
PORT 2 (O)
t
LHLL
t
AVLL
t
LLPL
t
PLPH
t
LLIV
t
PLIV
t
PLAZ
t
LLAX
t
PXIX
t
PXIZ
t
PHAX
t
AVIV
PCL (OUT)
INSTRUCTION
(IN)
PCH
02987-088
Figure 5. External Program Memory Read Cycle