Datasheet

ADuC832 Data Sheet
Rev. B | Page 10 of 92
TIMING SPECIFICATIONS
AV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2. Clock Input (External Clock Applied on XTAL1)
32.768 kHz External Crystal
Parameter
1, 2, 3
Description Min Typ Max Unit
t
CK
XTAL1 period (see Figure 3) 30.52 μs
t
CKL
XTAL1 width low (see Figure 3) 15.16 μs
t
CKH
XTAL1 width high (see Figure 3) 15.16 μs
t
CKR
XTAL1 rise time (see Figure 3) 20 ns
t
CKF
XTAL1 fall time (see Figure 3) 20 ns
1/t
CORE
ADuC832 core clock frequency
4
0.131 16.78 MHz
t
CORE
ADuC832 core clock period
5
0.476 μs
t
CYC
ADuC832 machine cycle time
6
0.72 5.7 91.55 μs
1
AC inputs during testing are driven at DV
DD
− 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at V
IH
minimum for a Logic 1 and V
IL
maximum for
a Logic 0, as shown in Figure 4.
2
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded V
OH
/V
OL
level occurs, as shown in Figure 4.
3
C
LOAD
for all outputs = 80 pF, unless otherwise noted.
4
The ADuC832 internal PLL locks onto a multiple (512 times) the external crystal frequency of 32.768 kHz to provide a stable 16.78 MHz internal clock for the system.
The core can operate at this frequency or at a binary submultiple called Core_CLK, selected via the PLLCON SFR.
5
This number is measured at the default Core_CLK operating frequency of 2.09 MHz.
6
ADuC832 machine cycle time is nominally defined as 12/Core_CLK.
t
CKH
t
CKL
t
CK
t
CKF
t
CKR
0
2987-086
Figure 3. XTAL1 Input
DV
DD
–0.5
V
0.45V
0.2DV
DD
+ 0.9V
TEST POINTS
0.2DV
DD
– 0.1V
V
LOAD
– 0.1V
V
LOAD
V
LOAD
+ 0.1V
TIMING
REFERENCE
POINTS
V
LOAD
– 0.1V
V
LOAD
V
LOAD
+ 0.1V
0
2987-087
Figure 4. Timing Waveform Characteristics