FEATURES FUNCTIONAL BLOCK DIAGRAM ANALOG I/O 8-channel, 247 kSPS, 12-Bit ADC DC performance: ±1 LSB INL AC performance: 71 dB SNR DMA controller for high speed ADC-to-RAM capture 2 12-bit (monotonic) voltage output DACs Dual output PWM/Σ-Δ DACs On-chip temperature sensor function: ±3°C On-chip voltage reference Memory 62 kB on-chip Flash/EE program memory 4 kB on-chip Flash/EE data memory Flash/EE, 100 Yr retention, 100,000 cycles of endurance 2304 bytes on-chip data RAM 8051-based core 8051-compatible in
ADuC832 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Initiating Calibration in Code ...................................................... 44 Applications ....................................................................................... 1 Nonvolatile Flash/EE Memory ..................................................... 45 Functional Block Diagram .............................................................
Data Sheet ADuC832 Dual Data Pointers ..........................................................................62 SCON (UART Serial Port Control Register) ........................... 75 DPCON (Data Pointer Control SFR) .......................................62 Mode 0: 8-Bit Shift Register Mode ........................................... 76 Power Supply Monitor ....................................................................63 Mode 1: 8-Bit UART, Variable Baud Rate ...............................
ADuC832 Data Sheet REVISION HISTORY 4/13—Rev. A to Rev. B Updated Outline Dimensions ....................................................... 89 Changes to Ordering Guide .......................................................... 89 9/09—Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changed 16.77 MHz to 16.78 MHz Throughout .........................
Data Sheet ADuC832 diagram of the ADuC832 is shown in Figure 1 with a more detailed block diagram shown in Figure 2. On-chip factory firmware supports in-circuit serial download and debug modes (via UART) as well as single-pin emulation mode via the EA pin. The ADuC832 is supported by QuickStart™ and QuickStart Plus development systems featuring low cost software and hardware development tools.
ADuC832 Data Sheet SPECIFICATIONS AVDD = DVDD = 2.7 V to 3.3 V or 4.5 V to 5.5 V; VREF = 2.5 V internal reference, fCORE = 16.78 MHz; all specifications TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1 ADC CHANNEL SPECIFICATIONS DC Accuracy 2, 3 VDD = 5 V Resolution Integral Nonlinearity 12 ±1 ±0.3 ±0.9 ±0.25 ±1.5 +1.5/−0.9 1 12 ±1 ±0.3 ±0.9 ±0.25 ±1.5 +1.5/−0.
Data Sheet Parameter 1 DAC CHANNEL SPECIFICATIONS 12, 13, INTERNAL BUFFER DISABLED DC Accuracy10 Resolution Relative Accuracy Differential Nonlinearity11 Offset Error Gain Error Gain Error Mismatch4 Analog outputs Voltage Range 0 REFERENCE INPUT/OUTPUT Reference Output 14 Output Voltage (VREF) Accuracy Power Supply Rejection Reference Temperature Coefficient Internal VREF Power-On Time External Reference Input 15 Voltage Range (VREF)4 Input Impedance Input Leakage POWER SUPPLY MONITOR (PSM) DVDD Trip Point
ADuC832 Parameter 1 SCLOCK and RESET ONLY4 (Schmitt-Triggered Inputs) VT+ VT− VT+ − VT− CRYSTAL OSCILLATOR Logic Inputs, XTAL1 Only VINL, Input Low Voltage VINH, Input High Voltage XTAL1 Input Capacitance XTAL2 Output Capacitance MCU CLOCK RATE DIGITAL OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) ALE, Port 0 and Port 2 Port 3 SCLOCK/SDATA Floating State Leakage Current4 Floating State Output Capacitance START-UP TIME At Power-On From Idle Mode From Power-Down Mode Wakeup with INT0 Interrupt W
Data Sheet Parameter 1 Power Supply Currents Power-Down Mode DVDD Current4 AVDD Current DVDD Current Typical Additional Power Supply Currents PSM Peripheral ADC DAC ADuC832 VDD = 5 V VDD = 3 V Unit 80 38 2 35 25 25 14 1 20 12 μA max μA typ μA typ μA max μA typ Test Conditions/Comments Core_CLK = 2.097 MHz or 16.78 MHz Oscillator on Oscillator off AVDD = DVDD = 5 V 50 1.5 150 μA typ mA typ μA typ Temperature range: −40°C to +125°C.
ADuC832 Data Sheet TIMING SPECIFICATIONS AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Data Sheet ADuC832 Table 3. External Program Memory Read Cycle Parameter1 tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tPHAX Min 79 19 29 16.78 MHz Core_CLK Max 138 29 133 73 0 34 193 25 0 Variable Clock Min Max 2tCK − 40 tCK − 40 tCK − 30 4tCK − 100 tCK − 30 3tCK − 45 3tCK − 105 0 tCK − 25 5tCK − 105 25 0 See Figure 5.
ADuC832 Data Sheet Table 4. External Data Memory Read Cycle Parameter1 tRLRH tAVLL tLLAX tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tRLAZ tWHLH Variable Clock Min Max 6tCK − 100 tCK − 40 tCK − 35 5tCK − 165 0 2tCK − 70 8tCK − 150 9tCK − 165 3tCK − 50 3tCK +50 4tCK − 130 0 tCK − 40 6tCK − 100 See Figure 6.
Data Sheet ADuC832 Table 5. External Data Memory Write Cycle Parameter 1 tWLWH tAVLL tLLAX tLLWL tAVWL tQVWX tQVWH tWHQX tWHLH Variable Clock Min Max 6tCK − 100 tCK − 40 tCK − 35 3tCK − 50 3tCK +50 4tCK − 130 tCK − 50 7tCK − 150 tCK − 50 tCK − 40 6tCK − 100 See Figure 7. MCLK ALE (O) tWHLH PSEN (O) tLLWL tWLWH WR (O) tAVWL tAVLL tLLAX A0 TO A7 PORT 2 (O) A16 TO A23 tQVWX tWHQX tQVWH DATA A8 TO A15 Figure 7. External Data Memory Write Cycle Rev. B | Page 13 of 92 02987-090 1 16.
ADuC832 Data Sheet Table 6. UART Timing (Shift Register Mode) Parameter 1 tXLXL tQVXH tDVXH tXHDX tXHQX Variable Clock Typ 12tCK 10tCK − 133 2tCK + 133 0 2tCK − 117 Min Max See Figure 8. ALE (O) tXLXL TxD (OUTPUT CLOCK) 6 1 0 7 SET RI OR SET TI tQVXH tXHQX RxD (OUTPUT DATA) MSB BIT 6 BIT 1 tDVXH RxD (INPUT DATA) MSB LSB tXHDX BIT 6 Figure 8. UART Timing in Shift Register Mode Rev. B | Page 14 of 92 BIT 1 LSB 02987-091 1 16.
Data Sheet ADuC832 Table 7. I2C-Compatible Interface Timing Parameter 1 tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF tSUP 2 2 Min 4.7 4.0 0.6 100 Max Unit μs μs μs μs μs μs μs μs ns ns ns 0.9 0.6 0.6 1.3 300 300 50 See Figure 9. Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns. tBUF tSUP SDATA (I/O) LSB MSB tDSU tPSU tDSU 2–7 8 PS tL MSB tF tDHD tR tRSU tH 1 START STOP CONDITION CONDITION ACK tDHD tSHD SCLOCK (I) tR 1 9 tSUP Figure 9.
ADuC832 Data Sheet Table 8. SPI Master Mode Timing (CPHA = 1) Parameter1 tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF 2 Min Typ 476 476 Max Unit ns ns ns ns ns ns ns ns ns 50 100 100 10 10 10 10 25 25 25 25 See Figure 10. Characterized under the following conditions: a. Core clock divider bits (CD2, CD1, and CD0 bits in PLLCON SFR) set to 0, 1, and 1, respectively, that is, core clock frequency = 2.09 MHz b. SPI bit rate selection bits (SPR1 and SPR0 bits in SPICON SFR) set to 0 and 0, respectively.
Data Sheet ADuC832 Table 9. SPI Master Mode Timing (CPHA = 0) Parameter 1 tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF 2 Min Typ 476 476 Max Unit ns ns ns ns ns ns ns ns ns ns 50 150 100 100 10 10 10 10 25 25 25 25 See Figure 11. Characterized under the following conditions: a. Core clock divider bits (CD2, CD1, and CD0 bits in PLLCON SFR) set to 0, 1, and 1, respectively, that is, core clock frequency = 2.09 MHz b.
ADuC832 Data Sheet Table 10. SPI Slave Mode Timing (CPHA = 1) Parameter 1 tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS Min 0 Typ Max 330 330 50 100 100 10 10 10 10 25 25 25 25 0 See Figure 12.
Data Sheet ADuC832 Table 11. SPI Slave Mode Timing (CPHA = 0) Parameter 1 tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOSS tSFS Min 0 Typ Max 330 330 50 100 100 10 10 10 10 25 25 25 25 20 0 See Figure 13.
ADuC832 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 12.
Data Sheet ADuC832 P1.0/ADC0/T2 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 DVDD DGND P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 ALE PSEN EA PSEN EA P0.1/AD1 P0.0/AD0 ALE P0.5/AD5 P0.4/AD4 DVDD DGND P0.3/AD3 P0.2/AD2 P0.7/AD7 P0.6/AD6 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P2.7/PWM1/A15/A23 PIN 1 IDENTIFIER 38 P2.6/PWM0/A14/A22 37 P2.5/A13/A21 P1.1/ADC1/T2EX P1.2/ADC2 P1.3/ADC3 AVDD AVDD AGND AGND AGND CREF VREF DAC0 DAC1 P1.4/ADC4 P1.5/ADC5/SS 36 P2.
ADuC832 Data Sheet Mnemonic VREF Pin No. MQFP LFCSP 8 10 Type I/O DAC0 DAC1 P1.4/ADC4 9 10 11 11 12 13 O O I P1.5/ADC5/SS 12 14 I I P1.6/ADC6 13 15 I I I P1.7/ADC7 14 16 I I RESET 15 17 I I P3.0/RxD 16 18 I/O 17 19 P G Digital Ground. Ground reference point for the digital circuitry. I/O O P3.2/INT0 18 20 I I P3.3/INT1/MISO/PWM1 19 21 I I I/O O DVDD DGND 20, 34, 48 21, 35, 47 22, 36, 51 23, 37, 38, 50 Input Port 1 (P1.7). Port 1 is an 8-bit input port only.
Data Sheet Mnemonic P3.4/T0/PWMC/PWM0/EXTCLK ADuC832 Pin No. MQFP LFCSP 22 24 Type I/O I I O I P3.5/T1/CONVST 23 25 I/O I I P3.6/WR 24 26 I/O O P3.7/RD 25 27 SCLOCK SDATA/MOSI 26 27 28 29 P2.0/A8/A16 28 30 O O I/O I/O I/O I/O I/O P2.1/A9/A17 29 31 I/O I/O P2.2/A10/A18 30 32 I/O I/O P2.3/A11/A19 31 33 I/O I/O XTAL1 32 34 I Description Input/Output Port 3 (P3.4). Port 3 is a bidirectional port with internal pull-up resistors.
ADuC832 Mnemonic XTAL2 P2.4/A12/A20 Data Sheet Pin No. MQFP LFCSP 33 35 36 39 Type O I/O I/O P2.5/A13/A21 37 40 I/O I/O P2.6/PWM0/A14/A22 38 41 I/O O I/O P2.7/PWM1/A15/A23 39 42 I/O O I/O EA 40 43 I PSEN 41 44 O ALE 42 45 O P0.0/AD0 43 46 I/O I/O P0.1/AD1 44 47 I/O I/O Description Output of the Inverting Oscillator Amplifier. Input/Output Port 2 (P2.4). Port 2 is a bidirectional port with internal pull-up resistors.
Data Sheet ADuC832 Mnemonic P0.2/AD2 Pin No. MQFP LFCSP 45 48 Type I/O P0.3/AD3 46 I/O 49 I/O P0.4/AD4 49 52 I/O I/O P0.5/AD5 50 53 I/O I/O P0.6/AD6 51 54 I/O I/O P0.7/AD7 52 56 I/O Description Input/Output Port 0 (P0.2). Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs. External Memory Address and Data (AD2).
ADuC832 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.8 AVDD/DVDD = 5V fS = 152kHz 0.8 0.8 0.6 AVDD/DVDD = 3V fS = 152kHz 0.6 0.4 WCP INL 0.4 0.2 0 –0.2 0.2 0.2 0 0 WCN INL –0.2 –0.2 WCN–INL (LSB) 0.4 WCP–INL (LSB) TYPICAL INL ERROR (LSB) 0.6 –0.4 –0.4 –0.4 –0.6 –0.6 –0.6 0 511 1023 2559 2047 1535 ADC CODES 3583 3071 4095 –0.8 02987-005 –1.0 –0.8 0.5 Figure 16. Typical INL Error, VDD = 5 V 1.0 AVDD/DVDD = 3V fS = 152kHz 0.8 AVDD/DVDD = 5V fS = 152kHz 0.
Data Sheet ADuC832 0.6 10,000 0.6 AVDD/DVDD = 5V fS = 152kHz 7000 0 –0.2 OCCURRENCE 0.2 0 –0.2 8000 WCN–DNL (LSB) WCP DNL 0.2 WCP–DNL (LSB) 9000 0.4 0.4 –0.4 –0.6 –0.6 5000 4000 3000 WCN DNL –0.4 6000 2000 1000 5.0 0 817 0.5 821 AVDD/DVDD = 5V fS = 152kHz fIN = 9.910kHz 0 0.5 SNR = 71.3dB THD = –88.0dB ENOB = 11.6 –20 WCP DNL 0.3 0.3 820 20 0.7 AVDD/DVDD = 3V fS = 152kHz 819 CODE Figure 25. Code Histogram Plot, VDD = 3 V Figure 22.
ADuC832 Data Sheet –70 80 80 AVDD/DVDD = 5V AVDD/DVDD = 5V fS = 152kHz 78 –75 75 76 SNR THD –85 60 –90 55 –95 72 SNR (dB) 65 THD (dB) SNR (dB) 74 –80 70 70 68 66 64 50 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) 60 65.476 02987-017 –100 0.5 5.0 0.75 SENSOR VOLTAGE OUTPUT (V) –75 SNR –85 60 –90 55 –95 199.41 226.19 AVDD/DVDD = 3V SLOPE = –2mV/°C 0.70 0.65 0.60 0.55 0.50 –100 50 0.5 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) 3.0 0.
Data Sheet ADuC832 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
ADuC832 Data Sheet EXPLANATION OF TYPICAL PERFORMANCE PLOTS The plots presented in the Typical Performance Characteristics section illustrate typical performance of the ADuC832 under various operating conditions. Figure 16 and Figure 17 show typical ADC integral nonlinearity (INL) errors from ADC Code 0 to Code 4095 at 5 V and 3 V supplies, respectively. The ADC is using its internal reference (2.
Data Sheet ADuC832 MEMORY ORGANIZATION The ADuC832 contains four different memory blocks: 62 kB of on-chip Flash/EE program memory 4 kB of on-chip Flash/EE data memory 256 bytes of general-purpose RAM 2 kB of internal XRAM FLASH/EE PROGRAM MEMORY 7FH The ADuC832 provides 62 kB of Flash/EE program memory to run user code. The user can choose to run code from this internal memory or from an external program memory.
ADuC832 Data Sheet EXTERNAL DATA MEMORY (EXTERNAL XRAM) FFFFFFH FFFFFFH Similar to a standard 8051-compatible core, the ADuC832 can access external data memory using a MOVX instruction. The MOVX instruction automatically outputs the various control strobes required to access the data memory. EXTERNAL DATA MEMORY SPACE (24-BIT ADDRESS SPACE) EXTERNAL DATA MEMORY SPACE (24-BIT ADDRESS SPACE) The ADuC832, however, can access up to 16 MB of external data memory.
Data Sheet ADuC832 SPECIAL FUNCTION REGISTERS (SFRS) The SFR space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC832 via the SFR area is shown in Figure 35. used to provide memory addresses for internal and external code access and external data access.
ADuC832 Data Sheet SPECIAL FUNCTION REGISTERS that location. If an unoccupied location is read, an unspecified value is returned. SFR locations reserved for on-chip testing are shown lighter shaded in Figure 36 (labeled reserved) and should not be accessed by user software. Sixteen of the SFR locations are also bit addressable and denoted by Footnote 1 in Figure 36, that is, the bit addressable SFRs are those whose address ends in 0H or 8H.
Data Sheet ADuC832 ADC CIRCUIT INFORMATION GENERAL OVERVIEW ADC TRANSFER FUNCTION The ADC conversion block incorporates a fast, 8-channel, 12-bit, single-supply ADC. This block provides the user with multichannel mux, track/hold, on-chip reference, calibration features, and an ADC. All components in this block are easily configured via a three-register SFR interface. The analog input range for the ADC is 0 V to VREF.
ADuC832 Data Sheet ADCCON1 (ADC Control SFR 1) SFR Address: EFH SFR Power-On Default Value: 00H Bit Addressable: No The ADCCON1 register controls conversion and acquisition times, hardware conversion modes, and power-down modes as detailed in Table 16. Table 16. ADCCON1 SFR Bit Designations Bit [7] Name MD1 [6] [5] [4] EXT_REF CK1 CK0 [3:2] AQ[1:0] [1] T2C [0] EXC Description The mode bit selects the active operating mode of the ADC. Set by the user to power up the ADC.
Data Sheet ADuC832 ADCCON2 (ADC Control SFR 2) SFR Address: D8H SFR Power-On Default Value: 00H Bit Addressable: Yes The ADCCON2 register controls ADC channel selection and conversion modes as detailed in Table 17. Table 17. ADCCON2 SFR Bit Designations Bit [7] Name ADCI [6] DMA [5] CCONV [4] SCONV [3:0] CS[3:0] Description The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block conversion.
ADuC832 Data Sheet ADCCON3 (ADC Control SFR 3) SFR Address: F5H SFR Power-On Default Value: 00H Bit Addressable: No The ADCCON3 register controls the operation of various calibration modes as well as giving an indication of ADC busy status. Table 18. ADCCON3 SFR Bit Designations Bit [7] Name Busy [6] [5:4] GNCLD AVGS[1:0] [3] [2] [1] RSVD RSVD Typical [0] SCAL Description The ADC busy status bit is a read-only status bit that is set during a valid ADC conversion or calibration cycle.
Data Sheet ADuC832 The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. Figure 39 shows the equivalent circuit of the analog input section. Each ADC conversion is divided into two distinct phases as defined by the position of the switches in Figure 39. During the sampling phase (with SW1 and SW2 in the track position), a charge proportional to the voltage on the analog input is developed across the input sampling capacitor.
ADuC832 Data Sheet Table 20. Some Single-Supply Op Amps Op Amp Model OP281/OP481 OP191/OP291/OP491 OP196/OP296/OP496 OP183/OP249 OP162/OP262/OP462 AD820/AD822/AD824 AD823 Characteristics Micropower I/O Good up to VDD, low cost I/O to VDD, micropower, low cost High gain-bandwidth product (GBP) High GBP, micro package FET input, low cost FET input, high GBP Keep in mind that the ADC’s transfer function is 0 V to VREF, and any signal range lost to amplifier saturation near ground impacts dynamic range.
Data Sheet ADuC832 cannot sustain the interrupt rate, an ADC DMA mode is provided. ADuC832 51Ω VDD EXTERNAL VOLTAGE REFERENCE To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be set. This allows the ADC results to be written directly to a 16 MB external static memory SRAM (mapped into data memory space) without any interaction from the ADuC832 core. This mode allows the ADuC832 to capture a contiguous sample stream at full ADC update rates (247 kSPS). 2.
ADuC832 Data Sheet When the DMA conversions are completed, the ADC interrupt bit, ADCI, is set by hardware and the external SRAM contains the new ADC conversion results as shown in Figure 45. Note that no result is written to the last two memory locations. When the DMA mode logic is active, it takes the responsibility of storing the ADC results away from both the user and ADuC832 core logic.
Data Sheet ADuC832 CALIBRATING THE ADC There are two hardware calibration modes provided that can be easily initiated by user software. The ADCCON3 SFR is used to calibrate the ADC. The typical bit (ADCCON3[1]) and the CS3 to CS0 bits (ADCCON2[3:0]) set up the calibration modes. Device calibration can be initiated to compensate for significant changes in operating conditions frequency, analog input range, reference voltage, and supply voltages.
ADuC832 Data Sheet INITIATING CALIBRATION IN CODE When calibrating the ADC using ADCCON1, the ADC should be set up into the configuration in which it will be used. The ADCCON3 register can then be used to set up the device and calibrate the ADC offset and gain.
Data Sheet ADuC832 NONVOLATILE FLASH/EE MEMORY FLASH/EE MEMORY OVERVIEW ADUC832 FLASH/EE MEMORY RELIABILITY The ADuC832 incorporates Flash/EE memory technology on chip to provide the user with nonvolatile, in-circuit, reprogrammable code and data memory space. Flash/EE memory is a relatively recent type of nonvolatile memory technology and is based on a single transistor cell architecture.
ADuC832 Data Sheet 300 User Download Mode (ULOAD) As shown in Figure 49, it is possible to use the 62 kB of Flash/EE program memory available to the user as one single block of memory. In this mode, all of the Flash/EE memory is read only to user code. 200 ADI SPECIFICATION 100 YEARS MIN. AT TJ = 55°C 150 100 0 40 50 60 70 80 90 TJ JUNCTION TEMPERATURE (°C) 100 110 02987-037 50 Figure 48.
Data Sheet ADuC832 FLASH/EE PROGRAM MEMORY SECURITY Secure Mode The ADuC832 facilitates three modes of Flash/EE program memory security. These modes can be independently activated, restricting access to the internal code space. These security modes can be enabled as part of serial download protocol as described in Technical Note uC004 or via parallel programming. The security modes available on the ADuC832 are described as follows.
ADuC832 Data Sheet BYTE 3 (0FFEH) BYTE 4 (0FFFH) BYTE 1 (0FF8H) BYTE 3 (0FFAH) BYTE 4 (0FFBH) 03H BYTE 1 (000CH) BYTE 2 (000DH) BYTE 3 (000EH) BYTE 4 (000FH) 02H BYTE 1 (0008H) BYTE 2 (0009H) BYTE 3 (000AH) BYTE 4 (000BH) 01H BYTE 1 (0004H) BYTE 2 (0005H) BYTE 3 (0006H) BYTE 4 (0007H) 00H BYTE 1 (0000H) BYTE 2 (0001H) BYTE 3 (0002H) BYTE 4 (0003H) EDATA3 SFR EDATA4 SFR 3FEH BYTE 2 (0FFDH) BYTE 2 (0FF9H) EDATA2 SFR Programming of either the Flash/EE data memory or the Flash/EE
Data Sheet ADuC832 EXAMPLE: PROGRAMMING THE FLASH/EE DATA MEMORY To program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other three bytes already in this page, a typical program of the Flash/EE data array includes the following steps: 1. 2. 3.
ADuC832 Data Sheet ADUC832 CONFIGURATION SFR (CFG832) CFG832 (ADuC832 Configuration SFR) The CFG832 SFR contains the necessary bits to configure the internal XRAM, external clock select, PWM output selection, DAC buffer, and the extended SP. By default, it configures the user into 8051 mode; that is, extended SP is disabled and the internal XRAM is disabled. SFR Address: AFH Power-On Default Value: 00H Bit Addressable: No Table 24.
Data Sheet ADuC832 USER INTERFACE TO OTHER ON-CHIP ADUC832 PERIPHERALS The following section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DACxH/DACxL (DAC Data Registers) Function: DAC data registers, written by user to update the DAC output SFR Address: DAC0L (DAC0 data low byte) = F9H; DAC1L (DAC1 data low byte) = FBH DAC The ADuC832 incorporates two 12-bit voltage output DACs on chip.
ADuC832 Data Sheet AVDD USING THE DAC The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 51. Details of the actual DAC architecture can be found in U.S. Patent Number 5,969,657. Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity. AVDD –100mV ADuC832 AVDD 100mV R 0mV R FFFH 000H DAC0 02987-041 50mV OUTPUT BUFFER Figure 52.
Data Sheet ADuC832 4 To drive significant loads with the DAC outputs, external buffering may be required (even with the internal buffer enabled), as illustrated in Figure 55. A list of recommended op amps is shown in Table 20. OUTPUT VOLTAGE (V) DAC LOADED WITH 0FFFH 3 DAC0 1 ADuC832 DAC1 0 5 10 SOURCE/SINK CURRENT (mA) 15 02987-043 0 02987-044 DAC LOADED WITH 0000H Figure 55. Buffering the DAC Outputs Figure 54.
ADuC832 Data Sheet ON-CHIP PLL The ADuC832 is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (512) of this to provide a stable 16.78 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power saving in cases where maximum core performance is not required. The default core clock is the PLL clock divided by 8 or 2.097152 MHz.
Data Sheet ADuC832 PULSE-WIDTH MODULATOR (PWM) The PWM on the ADuC832 is a highly flexible PWM offering programmable resolution and an input clock, and can be configured for any one of six different modes of operation. Two of these modes allow the PWM to be configured as a Σ-Δ DAC with up to 16 bits of resolution. A block diagram of the PWM is shown in Figure 56. fVCO T0/EXTERNAL PWM CLOCK fXTAL /15 CLOCK SELECT PROGRAMMABLE DIVIDER fXTAL 16-BIT PWM COUNTER P2.
ADuC832 Data Sheet PWM MODES OF OPERATION MODE 0: PWM DISABLED PWM1L PWM COUNTER The PWM is disabled, allowing P2.6 and P2.7 to be used as normal. PWM0H MODE 1: SINGLE VARIABLE RESOLUTION PWM PWM0L In Mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the PWM to be variable. PWM0H/PWM0L sets the duty cycle of the PWM output waveform, as shown in Figure 57. P2.6 P2.7 Figure 58.
Data Sheet ADuC832 MODE 4: DUAL NRZ 16-BIT Σ-Δ DAC PWM1L PWM COUNTERS Mode 4 provides a high speed PWM output similar to that of a Σ-Δ DAC. Typically, this mode is used with the PWM clock equal to 16.777216 MHz. PWM1H PWM0L PWM0H In this mode, P2.6 and P2.7 are updated every PWM clock (60 ns in the case of 16 MHz). Over every 65,536 cycles (16-bit PWM) PWM0 (P2.6) is high for PWM0H/PWM0L cycles and low for (65,536 − PWM0H/L) cycles. Similarly PWM1 (P2.
ADuC832 Data Sheet SERIAL PERIPHERAL INTERFACE The ADuC832 integrates a complete hardware serial peripheral interface (SPI) on chip. SPI is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, that is, full duplex. It should be noted that the SPI pins are shared with the I2C pins. Therefore, the user can only enable one or the other interface at any given time (see SPE in Table 28).
Data Sheet ADuC832 SPIDAT (SPI Data Register) SPI INTERFACE—MASTER MODE SFR Address: F7H Power-On Default Value: 00H Bit Addressable: No In master mode, the SCLOCK pin is always an output and generates a burst of eight clocks whenever user code writes to the SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS pin is not used in master mode.
ADuC832 Data Sheet I2C-COMPATIBLE INTERFACE The ADuC832 supports a fully licensed I2C serial interface. The I2C interface is implemented as a full hardware slave and software master. SDATA is the data I/O pin and SCLOCK is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface. Therefore, the user can only enable one interface or the other at any given time (see SPE in SPICON in Table 28).
Data Sheet ADuC832 OVERVIEW The main features of the MicroConverter I2C interface are: • • • Only two bus lines are required; a serial data line (SDATA) and a serial clock line (SCLOCK). An I2C master can communicate with multiple slave devices. Because each slave device has a unique 7-bit address, single master/slave relationships can exist at all times even in a multislave environment (Figure 64). On-chip filtering rejects <50 ns spikes on the SDATA and the SCLOCK lines to preserve data integrity.
ADuC832 Data Sheet DUAL DATA POINTERS The ADuC832 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON also includes features such as automatic hardware postincrement and postdecrement, as well as automatic data pointer toggle. DPCON is described in Table 30. DPCON (DATA POINTER CONTROL SFR) SFR Address: A7H Power-On Default Value: 00H Bit Addressable: No Table 30.
Data Sheet ADuC832 POWER SUPPLY MONITOR As its name suggests, the power supply monitor, once enabled, monitors the DVDD supply on the ADuC832. It indicates when any of the supply pins drop below one of four user-selectable voltage trip points from 2.63 V to 4.37 V. For correct operation of the power supply monitor function, AVDD must be equal to or greater than 2.7 V. The monitor function is controlled via the PSMCON SFR.
ADuC832 Data Sheet WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC832 enters an erroneous state, possibly due to a programming error or electrical noise. The watchdog function can be disabled by clearing the watchdog enable (WDE) bit in the watchdog control (WDCON) SFR.
Data Sheet ADuC832 TIME INTERVAL COUNTER (TIC) Six SFRs are associated with the time interval counter, TIMECON being its control register. Depending on the configuration of the ITS0 and ITS1 bits in TIMECON, the selected time counter register overflow clocks the interval counter. When this counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON[2]) is set and generates an interrupt if enabled.
ADuC832 Data Sheet INTVAL (USER TIME INTERVAL SELECT REGISTER) MIN (MINUTES TIME REGISTER) SFR Address: A6H SFR Address: A4H Power-On Default Value: 00H Power-On Default Value: 00H Bit Addressable: No Bit Addressable: No Valid Value: 0 to 255 decimal Valid Value: 0 to 59 decimal User code writes the required time interval to this register.
Data Sheet ADuC832 8052-COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary peripheral circuits that are also available to the user on chip. These remaining functions are mostly 8052 compatible (with a few additional features) and are controlled via standard 8052 SFR bit definitions. NAND gate whose output remains high as long as the control signal is low, thereby disabling the top FET.
ADuC832 Data Sheet them drive a logic low output voltage (VOL) and are capable of sinking 1.6 mA. P2.6 and P2.7 can also be used as PWM outputs. If they are selected as the PWM outputs via the CFG832 SFR, the PWM outputs overwrite anything written to P2.6 or P2.7. ADDR CONTROL INTERNAL BUS WRITE TO LATCH DVDD DVDD Q CL Q READ PIN P2.x PIN 02987-057 LATCH READ PIN *SEE FIGURE 69 FOR DETAILS OF INTERNAL PULL-UP Figure 68.
Data Sheet ADuC832 HARDWARE I 2C (SLAVE ONLY) SFR BITS MISO is shared with P3.3 and as such has the same configuration as that shown in Figure 70. DVDD SPE = 0 (I2C ENABLE) Q1 (OFF) READ-MODIFY-WRITE INSTRUCTIONS Q2 50ns GLITCH REJECTION FILTER Some 8051 instructions that read a port read the latch while others read the pin. The instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and then rewrite it to the latch.
ADuC832 Data Sheet TIMERS/COUNTERS The ADuC832 has three 16-bit timer/counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware has been included on chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers THx and TLx (x = 0, 1, and 2). All three can be configured to operate either as timers or event counters. In the timer function, the TLx register is incremented every machine cycle.
Data Sheet ADuC832 TCON (Timer/Counter 0 and Timer/Counter 1 Control Register) TIMER/COUNTER 0 AND TIMER/COUNTER 1 DATA REGISTERS SFR Address: 88H Power-On Default Value: 00H Each timer consists of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register, depending on the timer mode configuration. Bit Addressable: Yes TH0 and TL0 TH0 is the Timer 0 high byte and TL0 is the low byte. The SFR addresses for TH0 and TL0 are 8CH and 8AH, respectively.
ADuC832 Data Sheet TIMER/COUNTER 0 AND TIMER/COUNTER 1 OPERATING MODES MODE 2 (8-BIT TIMER/COUNTER WITH AUTORELOAD) The following sections describe the operating modes for Timer/Counter 0 and Timer/Counter 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for Timer 0 as for Timer 1. Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 77.
Data Sheet ADuC832 TIMER/COUNTER 2 T2CON (TIMER/COUNTER 2 CONTROL REGISTER) TIMER/COUNTER 2 DATA REGISTERS SFR Address: C8H Power-On Default Value: 00H Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and timer capture/reload registers. Bit Addressable: Yes TH2 and TL2 TH2 is the Timer 2 data high byte and TL2 is the low byte. The SFR addresses for TH2 and TL2 are CDH and CCH, respectively.
ADuC832 Data Sheet 16-Bit Capture Mode TIMER/COUNTER OPERATION MODES In the capture mode, there are again two options, which are selected by Bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter that, upon overflowing, sets Bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt.
Data Sheet ADuC832 UART SERIAL INTERFACE The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, the first byte is lost.
ADuC832 Data Sheet MODE 0: 8-BIT SHIFT REGISTER MODE Mode 0 is selected by clearing both the SM0 and SM1 bits in the SCON SFR. Serial data enter and exit through RxD. TxD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. The data is shifted out of the RxD line. The eight bits are transmitted with the least significant bit (LSB) first, as shown in Figure 81.
Data Sheet ADuC832 UART SERIAL PORT BAUD RATE GENERATION TIMER 2 GENERATED BAUD RATES Mode 0 Baud Rate Generation The baud rate in Mode 0 is fixed. Mode 0 Baud Rate = (Core_CLK Frequency/12) Mode 2 Baud Rate Generation The baud rate in Mode 2 depends on the value of the SMOD bit in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the core clock.
ADuC832 Data Sheet TIMER 1 OVERFLOW 2 OSC. FREQ. IS DIVIDED BY 2, NOT 12. 0 CORE CLK* 1 SMOD CONTROL 2 C/T2 = 0 TL2 (8 BITS) TIMER 2 OVERFLOW TH2 (8 BITS) 1 0 RCLK C/T2 = 1 T2 PIN 16 1 RX CLOCK 0 TR2 TCLK NOTE AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT RELOAD 16 RCAP2L T2EX PIN TX CLOCK RCAP2H TIMER 2 INTERRUPT EXF 2 02987-071 CONTROL TRANSITION DETECTOR EXEN2 *CORE CLK IS DEFINED BY THE CD BITS IN PLLCON. Figure 83.
Data Sheet ADuC832 After the values for DIV and T3FD are calculated, the actual baud rate can be calculated using the following formula: Actual Baud Rate = Table 44. Commonly Used Baud Rates Using Timer 3 2 × f CORE 2 DIV × (T 3FD + 64) For example, to obtain a baud rate of 115,200 while operating at 16.78 MHz, DIV = log(11,059,200/(32 × 115,200))/log(2) = 1.58 = 1 T3FD = (2 × 11,059,200)/(21 × 115,200) − 64 = 32 = 20H Therefore, the actual baud rate is 114,912 bits/sec.
ADuC832 Data Sheet INTERRUPT SYSTEM The ADuC832 provides a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs: IE (INTERRUPT ENABLE REGISTER) SFR Address: A8H • • • Power-On Default Value: 00H Bit Addressable: Yes IE—interrupt enable register IP—interrupt priority register IEIP2—secondary interrupt enable register Table 45.
Data Sheet ADuC832 INTERRUPT PRIORITY INTERRUPT VECTORS The interrupt enable registers are written by the user to enable individual interrupt sources, whereas the interrupt priority registers allow the user to select one of two priority levels for each interrupt. An interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt is serviced first.
ADuC832 Data Sheet ADUC832 HARDWARE DESIGN CONSIDERATIONS A second very important function of the EA pin is described in the Single Pin Emulation Mode section. This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC832 into any hardware system. CLOCK OSCILLATOR The clock source for the ADuC832 can be generated by the internal PLL or by an external clock input. To use the internal PLL, connect a 32.
Data Sheet ADuC832 avoid damaging the chip (as per the Absolute Maximum Ratings section). Therefore, it is recommended that, unless AVDD and DVDD are connected directly together, back-to-back Schottky diodes be connected between them as shown in Figure 90. SRAM ADuC832 D0 TO D7 (DATA) P0 LATCH A0 TO A7 ALE ANALOG SUPPLY DIGITAL SUPPLY 10µF 10µF P2 A8 TO A15 RD OE WR WE 02987-076 ADuC832 DVDD AVDD DGND AGND 0.1µF 0.1µF Figure 88.
ADuC832 Data Sheet The currents consumed by the various sections of the ADuC832 are shown in Table 50. The core values given represent the current drawn by DVDD, and the rest (ADC, DAC, voltage reference) are pulled by the AVDD pin and can be disabled in software when not in use. The other on-chip peripherals (for example, watchdog timer and power supply monitor) consume negligible current and are therefore included with the core operating current.
Data Sheet ADuC832 As with all high resolution data converters, special attention must be paid to grounding and PCB layout of ADuC832- based designs to achieve optimum performance from the ADC and DACs. Although the ADuC832 has separate pins for analog and digital ground (AGND and DGND), the user must not tie these to two separate ground planes unless the two ground planes are connected together very close to the ADuC832, as illustrated in the simplified example of Figure 93a.
ADuC832 Data Sheet DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) DVDD DVDD 1kΩ 1kΩ 46 45 44 43 42 2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN) 41 40 EA P1.0ADC0/T2 ANALOG INPUT 47 48 PSEN 49 DVDD 50 DGND 51 52 39 38 37 AVDD 36 AVDD AGND VREF OUTPUT DVDD 34 ADuC832 CREF XTAL2 33 VREF XTAL1 32 16 14 32.768kHz DVDD 18 19 DGND 29 P3.1/TxD P3.0/RxD P1.
Data Sheet ADuC832 OTHER HARDWARE CONSIDERATIONS To facilitate in-circuit programming, plus in-circuit debug and emulation options, implement some simple connection points in the hardware that allow easy access to download, debug, and emulation modes. IN-CIRCUIT SERIAL DOWNLOAD ACCESS Nearly all ADuC832 designs can take advantage of the in-circuit reprogrammability of the chip.
ADuC832 Data Sheet DEVELOPMENT TOOLS Download—In-Circuit Serial Downloader There are two models of development tools available for the ADuC832. • • QuickStart—entry-level development system QuickStart Plus—comprehensive development system QUICKSTART DEVELOPMENT SYSTEM The QuickStart development system is an entry-level, low cost development tool suite supporting the ADuC832. The system consists of the following PC-based (Windows® compatible) hardware and software development tools. Table 51.
Data Sheet ADuC832 OUTLINE DIMENSIONS 14.15 13.90 SQ 13.65 2.45 MAX 1.03 0.88 0.73 27 39 26 40 SEATING PLANE 7.80 REF TOP VIEW 2.10 2.00 1.95 0.23 0.11 VIEW A PIN 1 52 7° 0° 0.25 MIN 10.20 10.00 SQ 9.80 (PINS DOWN) 10° 6° 2° 14 13 1 0.10 COPLANARITY 0.38 0.22 LEAD WIDTH 0.65 BSC LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MO-112-AC-1 Figure 95. 52-Lead Metric Quad Flat Package [MQFP] (S-52-2) Dimensions shown in millimeters 0.30 0.23 0.18 0.60 MAX 0.
ADuC832 Data Sheet NOTES Rev.
Data Sheet ADuC832 NOTES Rev.
ADuC832 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Philips I2C Patent Rights to use the ADuC832 in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2002–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02987-0-4/13(B) Rev.
