Datasheet

REV. 0–72–
ADuC831
Parameter Min Typ Max Unit Figure
SPI MASTER MODE TIMING (CPHA = 1)
t
SL
SCLOCK Low Pulsewidth 330 ns 75
t
SH
SCLOCK High Pulsewidth 330 ns 75
t
DAV
Data Output Valid after SCLOCK Edge 50 ns 75
t
DSU
Data Input Setup Time before SCLOCK Edge 100 ns 75
t
DHD
Data Input Hold Time after SCLOCK Edge 100 ns 75
t
DF
Data Output Fall Time 10 25 ns 75
t
DR
Data Output Rise Time 10 25 ns 75
t
SR
SCLOCK Rise Time 10 25 ns 75
t
SF
SCLOCK Fall Time 10 25 ns 75
SCLOCK
(CPOL = 0)
t
DSU
SCLOCK
(CPOL = 1)
MOSI
MISO
MSB
LSB
LSB IN
BITS 6–1
BITS 6–1
t
DHD
t
DR
t
DAV
t
DF
t
SH
t
SL
t
SR
t
SF
MSB IN
Figure 75. SPI Master Mode Timing (CPHA = 1)