Datasheet

REV. 0–70–
ADuC831
12 MHz Variable Clock
Parameter Min Typ Max Min Typ Max Unit Figure
UART TIMING (Shift Register Mode)
t
XLXL
Serial Port Clock Cycle Time 1.0 12t
CK
µs73
t
QVXH
Output Data Setup to Clock 700 10t
CK
– 133 ns 73
t
DVXH
Input Data Setup to Clock 300 2t
CK
+ 133 ns 73
t
XHDX
Input Data Hold after Clock 0 0 ns 73
t
XHQX
Output Data Hold after Clock 50 2t
CK
– 117 ns 73
SET RI
OR
SET TI
0
BIT 1
t
XLXL
ALE (O)
TxD
(OUTPUT CLOCK)
RxD
(OUTPUT DATA)
RxD
(INPUT DATA)
1
BIT 6
MSB
MSB
BIT 6
BIT 1 LSB
t
XHQX
t
QVXH
t
DVXH
t
XHDX
6
7
LSB
Figure 73. UART Timing in Shift Register Mode