Datasheet

REV. 0
ADuC831
–69–
12 MHz Variable Clock
Parameter Min Max Min Max Unit Figure
EXTERNAL DATA MEMORY WRITE CYCLE
t
WLWH
WR Pulsewidth 400 6t
CK
– 100 ns 72
t
AVLL
Address Valid after ALE Low 43 t
CK
–40 ns 72
t
LLAX
Address Hold after ALE Low 48 t
CK
–35 ns 72
t
LLWL
ALE Low to RD or WR Low 200 300 3t
CK
–50 3t
CK
+50 ns 72
t
AVWL
Address Valid to RD or WR Low 203 4t
CK
– 130 ns 72
t
QVWX
Data Valid to WR Transition 33 t
CK
–50 ns 72
t
QVWH
Data Setup before WR 433 7t
CK
– 150 ns 72
t
WHQX
Data and Address Hold after WR 33 t
CK
–50 ns 72
t
WHLH
RD or WR High to ALE High 43 123 t
CK
–40 6t
CK
– 100 ns 72
t
LLAX
DATA
M
CLK
ALE (O)
PSEN (O)
PORT 2 (O)
t
LLWL
t
AVWL
t
AVLL
t
QVWX
t
WHQX
t
WHLH
A0–A7
A16–A23
A8–A15
t
WLWH
t
QVWH
WR (O)
Figure 72. External Data Memory Write Cycle