Datasheet

REV. 0–68–
ADuC831
12 MHz Variable Clock
Parameter Min Max Min Max Unit Figure
EXTERNAL DATA MEMORY READ CYCLE
t
RLRH
RD Pulsewidth 400 6t
CK
– 100 ns 71
t
AVLL
Address Valid after ALE Low 43 t
CK
–40 ns 71
t
LLAX
Address Hold after ALE Low 48 t
CK
–35 ns 71
t
RLDV
RD Low to Valid Data In 252 5t
CK
– 165 ns 71
t
RHDX
Data and Address Hold after RD 00 ns71
t
RHDZ
Data Float after RD 97 2t
CK
–70 ns 71
t
LLDV
ALE Low to Valid Data In 517 8t
CK
– 150 ns 71
t
AVDV
Address to Valid Data In 585 9t
CK
– 165 ns 71
t
LLWL
ALE Low to RD or WR Low 200 300 3t
CK
–50 3t
CK
+50 ns 71
t
AVWL
Address Valid to RD or WR Low 203 4t
CK
– 130 ns 71
t
RLAZ
RD Low to Address Float 0 0 ns 71
t
WHLH
RD or WR High to ALE High 43 123 t
CK
–40 6t
CK
– 100 ns 71
t
LLAX
DATA (IN)
M
CLK
ALE (O)
PSEN (O)
PORT 0 (I/O)
PORT 2 (O)
RD (O)
t
LLDV
t
LLWL
t
AVWL
t
AVLL
t
AVDV
t
RLAZ
t
RLDV
t
RHDX
t
RHDZ
t
WHLH
A0–A7
(OUT)
A16–A23
A8–A15
t
RLRH
Figure 71. External Data Memory Read Cycle