Datasheet

REV. 0
ADuC831
–67–
12 MHz Variable Clock
Parameter Min Max Min Max Unit Figure
EXTERNAL PROGRAM MEMORY READ CYCLE
t
LHLL
ALE Pulsewidth 127 2t
CK
–40 ns 70
t
AVLL
Address Valid to ALE Low 43 t
CK
–40 ns 70
t
LLAX
Address Hold after ALE Low 53 t
CK
–30 ns 70
t
LLIV
ALE Low to Valid Instruction In 234 4t
CK
– 100 ns 70
t
LLPL
ALE Low to PSEN Low 53 t
CK
–30 ns 70
t
PLPH
PSEN Pulsewidth 205 3t
CK
–45 ns 70
t
PLIV
PSEN Low to Valid Instruction In 145 3t
CK
– 105 ns 70
t
PXIX
Input Instruction Hold after PSEN 00 ns70
t
PXIZ
Input Instruction Float after PSEN 59 t
CK
–25 ns 70
t
AVIV
Address to Valid Instruction In 312 5t
CK
– 105 ns 70
t
PLAZ
PSEN Low to Address Float 25 25 ns 70
t
PHAX
Address Hold after PSEN High 0 0 ns 70
t
LHLL
t
AVLL
PCL
(OUT)
INSTRUCTION
(IN)
PCH
M
CLK
ALE (O)
PSEN (O)
PORT 0 (I/O)
PORT 2 (O)
t
LLPL
t
LLAX
t
PLAZ
t
PXIX
t
PXIZ
t
PLIV
t
LLIV
t
PLPH
t
PHAX
t
AVIV
Figure 70. External Program Memory Read Cycle