Datasheet

REV. 0
ADuC831
–31–
ADuC831 Configuration SFR (CFG831)
The CFG831 SFR contains the necessary bits to configure the
internal XRAM, EPROM controller, PWM output selection
and frequency, DAC buffer, and the extended SP. By default it
configures the user into 8051 mode, i.e., extended SP is disabled,
internal XRAM is disabled.
CFG831 ADuC831 Config SFR
SFR Address AFH
Power-On Default Value 10*H
Bit Addressable No
Table VIII. CFG831 SFR Bit Designations
Bit Name Description
7 EXSP Extended SP Enable.
When set to “1” by the user, the stack will rollover from SPH/SP = 00FFH to 0100H.
When set to “0” by the user, the stack will roll over from SP = FFH to SP = 00H.
6 PWPO PWM Pin Out Selection.
Set to “1” by the user = PWM output pins selected as P3.4 and P3.3.
Set to “0” by the user = PWM output pins selected as P2.6 and P2.7.
5 DBUF DAC Output Buffer.
Set to “1” by the user = DAC
.
Output Buffer Bypassed.
Set to “0” by the user = DAC Output Buffer Enabled.
4 EPM2 Flash/EE Controller and PWM Clock Frequency Configuration Bits.
3 EPM1 Frequency should be configured such that Fosc/Divide Factor = 32 kHz
+ 50%.
2 EPM0 EPM2 EPM1 EPM0 Divide Factor
000 32
001 64
010 128
011 256
100 512
101 1024
1 RSVD Reserved. This bit should always contain 0.
0 XRAMEN XRAM Enable Bit.
When set to “1” the internal XRAM will be mapped into the lower 2 kBytes of the external address space.
When set to “0” the internal XRAM will not be accessible and the external data memory will be mapped
into the lower 2 kBytes of external data memory.
*Note that the Flash/EE controller bits EPM2, EPM1, EPM0 are set to their
correct values depending on the crystal frequency at power-up. The user should
not modify these bits so all instructions to the CFG831 register should use the
ORL, XRL, or ANL instructions. Value of 10H is for a 11.0592 MHz crystal.