Datasheet

REV. 0–26–
ADuC831
INITIATING CALIBRATION IN CODE
When calibrating the ADC, using ADCCON1 the ADC should
be set up into the configuration in which it will be used. The
ADCCON3 register can then be used to set the device up and
calibrate the ADC offset and gain.
MOV ADCCON1,#08CH ;ADC on; ADCCLK set
;to divide by 16, 4
;acquisition clock
To calibrate device offset:
MOV ADCCON2,#0BH ;select internal AGND
MOV ADCCON3,#25H ;select offset calibration,
;31 averages per bit,
;offset calibration
To calibrate device gain:
MOV ADCCON2,#0CH ;select internal VREF
MOV ADCCON3,#27H ;select offset calibration,
;31 averages per bit,
;offset calibration
To calibrate system offset:
Connect system AGND to an ADC channel input (0).
MOV ADCCON2,#00H ;select external AGND
MOV ADCCON3,#25H ;select offset calibration,
;31 averages per bit
To calibrate system gain:
Connect system V
REF
to an ADC channel input (1).
MOV ADCCON2,#01H ;select external VREF
MOV ADCCON3,#27H ;select offset calibration,
;31 averages per bit,
;offset calibration
The calibration cycle time, T
CAL
, is calculated by the following
equation assuming a 16 MHz crystal:
T ADCCLK NUMAV T
CAL ACQ
=× × × +14 16()
For an ADCCLK/F
CORE
divide ratio of 16, a T
ACQ
= 4 ADCCLK,
NUMAV = 15, the calibration cycle time is:
T
T ms
CAL
CAL
=× × × +
=
14 1 1000000 15 16 4
42
(/ ) ( )
.
In a calibration cycle the ADC busy flag (Bit 7), instead of
framing an individual ADC conversion as in normal mode, will
go high at the start of calibration and only return to zero at the
end of the calibration cycle. It can therefore be monitored in
code to indicate when the calibration cycle is completed. The
following code can be used to monitor the BUSY signal during
a calibration cycle:
WAIT:
MOV A, ADCCON3 ;move ADCCON3 to A
JB ACC.7, WAIT ;If Bit 7 is set jump to
WAIT else continue