Datasheet

REV. 0
ADuC831
–19–
Table III. ADCCON1 SFR Bit Designations
Bit Name Description
ADCCON1.7 MD1 The Mode bit selects the active operating mode of the ADC.
Set by the user to power up the ADC.
Cleared by the user to power down the ADC.
ADCCON1.6 EXT_REF Set by the user to select an external reference.
Cleared by the user to use the internal reference.
ADCCON1.5 CK1 The ADC clock divide bits (CK1, CK0) select the divide ratio for the master clock used to generate the
ADCCON1.4 CK0 ADC clock. To ensure correct ADC operation, the divider ratio must be chosen to reduce the ADC clock
to 4.5 MHz and below. A typical ADC conversion will require 17 ADC clocks.
The divider ratio is selected as follows:
CK1 CK0 MCLK Divider
0016
012
104
118
ADCCON1.3 AQ1 The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track-and-hold amplifier
ADCCON1.2 AQ0 to acquire the input signal. An acquisition of three or more ADC clocks is recommended; clocks are
selected as follows:
AQ1 AQ0 #ADC Clks
001
012
103
114
ADCCON1.1 T2C The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 overflow bit be used as
the ADC convert start trigger input.
ADCCON1.0 EXC The external trigger enable bit (EXC) is set by the user to allow the external Pin P3.5 (CONVST) to
be used as the active low convert start input. This input should be an active low pulse (minimum
pulsewidth >100 ns) at the required sample rate.
ADCCON1 – (ADC Control SFR #1)
The ADCCON1 register controls conversion and acquisition
times, hardware conversion modes and power-down modes as
detailed below.
SFR Address: EFH
SFR Power-On Default Value: 00H
Bit Addressable: NO