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ADuC831

FEATURES

ANALOG I/O

8-Channel, 247 kSPS 12-Bit ADC

DC Performance: 1 LSB INL

AC Performance: 71 dB SNR

DMA Controller for High Speed ADC-to-RAM Capture

2 12-Bit (Monotonic) Voltage Output DACs

Dual Output PWM/- DACs

On-Chip Temperature Sensor Function 3C

On-Chip Voltage Reference

Memory

62 kBytes On-Chip Flash/EE Program Memory

4 kBytes On-Chip Flash/EE Data Memory

Flash/EE, 100 Yr Retention, 100 kCycles Endurance

2304 Bytes On-Chip Data RAM

8051 Based Core

8051 Compatible Instruction Set (16 MHz Max)

12 Interrupt Sources, 2 Priority Levels

Dual Data Pointer

Extended 11-Bit Stack Pointer

On-Chip Peripherals

Time Interval Counter (TIC)

UART, I

, and SPI

Serial I/O

Watchdog Timer (WDT), Power Supply Monitor (PSM)

Power

Specified for 3 V and 5 V Operation

Normal, Idle, and Power-Down Modes

Power-Down: 20 A @ 3 V

APPLICATIONS

Optical Networking—Laser Power Control

Base Station Systems

Precision Instrumentation, Smart Sensors

Transient Capture Systems

DAS and Communications Systems

Pin compatible upgrade to existing ADuC812 systems

that require additional code or data memory. Runs

from 1 MHz–16 MHz to external crystal.

The ADuC832 is also available. Functionally is the same

as the ADuC831, except the ADuC832 runs from a 32 kHz

external crystal with on-chip PLL.

MicroConverter is a registered trademark and QuickStart is a trademark

of Analog Devices, Inc.

SPI is a registered trademark of Motorola, Inc.

C is a registered trademark of Philips Corporation.

GENERAL DESCRIPTION

The ADuC831 is a fully integrated 247 kSPS data acquisition

system incorporating a high performance self-calibrating multi-

channel 12-bit ADC, dual 12-bit DACs, and programmable

8-bit MCU on a single chip.

The microcontroller core is an 8052, and therefore 8051-

instruction-set compatible with 12 core clock periods per machine

cycle. 62 kBytes of nonvolatile Flash/EE program memory are

provided on-chip. Four kBytes of nonvolatile Flash/EE data

memory, 256 bytes RAM and 2 kBytes of extended RAM are

also integrated on-chip.

The ADuC831 also incorporates additional analog functionality

with two 12-bit DACs, power supply monitor, and a band gap

reference. On-chip digital peripherals include two 16-bit Σ-∆

DACs, dual output 16-bit PWM, watchdog timer, time interval

counter, three timers/counters, Timer 3 for baud rate generation

and serial I/O ports (I

C, SPI and UART).

On-chip factory firmware supports in-circuit serial download and

debug modes (via UART), as well as single-pin emulation mode

via the EA pin. The ADuC831 is supported by QuickStart™ and

QuickStart Plus development systems featuring low cost software

and hardware development tools. A functional block diagram of

the ADuC831 is shown above with a more detailed block diagram

shown in Figure 1.

The part is specified for 3 V and 5 V operation over the extended

industrial temperature range, and is available in a 52-lead plastic

quad flatpack package and in a 56-lead chip scale package.

FUNCTIONAL BLOCK DIAGRAM

62 kBYTES FLASH/EE PROGRAM MEMORY

4 kBYTES FLASH/EE DATA MEMORY

2304 BYTES USER RAM

3  16 BIT TIMERS

1  REAL TIME CLOCK

PARALLEL

PORTS

8051-BASED MCU WITH ADDITIONAL

PERIPHERALS

ADuC831

XTAL2XTAL1

TEMP

SENSOR

REF

INTERNAL

BAND GAP

VREF

ADC0

ADC1

ADC5

ADC6

ADC7

OSC

12-BIT

DAC

PWM0

T/H

MUX

12-BIT ADC

HARDWARE

CALIBRATON

BUF

DAC

BUF

PWM1

12-BIT

DAC

16-BIT

- DAC

16-BIT

- DAC

16-BIT

PWM

16-BIT

PWM

POWER SUPPLY MON

WATCHDOG TIMER

UART, I

C, AND SPI

SERIAL I/O

MUX

MicroConverter

, 12-Bit ADCs and DACs

with Embedded 62 kBytes Flash MCU

Summary of content (76 pages)

PAGE 1
MicroConverter , 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU ADuC831 ® FEATURES ANALOG I/O 8-Channel, 247 kSPS 12-Bit ADC DC Performance: 1 LSB INL AC Performance: 71 dB SNR DMA Controller for High Speed ADC-to-RAM Capture 2 12-Bit (Monotonic) Voltage Output DACs Dual Output PWM/ - DACs On-Chip Temperature Sensor Function 3 C On-Chip Voltage Reference Memory 62 kBytes On-Chip Flash/EE Program Memory 4 kBytes On-Chip Flash/EE Data Memory Flash/EE, 100 Yr Retention, 100 kCycles Endurance 2304 B
PAGE 2
ADuC831 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Flash/EE Program Memory Security . . . . . . . . . . . . . . . . Using the Flash/EE Data Memory . . . . . . . . . . . . . . . . . . ECON—Flash/EE Memory Control SFR . . . . . . . . . . . . Flash/EE Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
ADuC831 = DV = 2.7 V to 3.3 V or 4.5 V to 5.5 V. V = 2.5 V Internal Reference, MCLKIN = 16 MHz, T = T to T , unless otherwise noted.
PAGE 4
ADuC831 SPECIFICATIONS (continued) Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments 12 ±3 –1 ± 1/2 ±5 –0.3 0.5 12 ±3 –1 ± 1/2 ±5 –0.3 0.5 Bits LSB typ LSB max LSB typ mV max % typ % max VREF Range VREF Range % of Full-Scale on DAC1 ANALOG OUTPUTS Voltage Range_0 0 to VREF 0 to VREF V typ DAC VREF = 2.5 V REFERENCE INPUT/OUTPUT REFERENCE OUTPUT14 Output Voltage (VREF) Accuracy Power Supply Rejection Reference Temperature Coefficient Internal VREF Power-On Time 2.5 ± 2.
PAGE 5
ADuC831 Parameter VDD = 5 V VDD = 3 V Unit 1.3 3.0 0.8 1.4 0.3 0.85 0.95 2.5 0.4 1.1 0.3 0.85 V min V max V min V max V min V max Test Conditions/Comments 4 SCLOCK and RESET Only (Schmitt-Triggered Inputs) VT+ VT– VT+ – VT– CRYSTAL OSCILLATOR Logic Inputs, XTAL1 Only VINL, Input Low Voltage VINH, Input High Voltage XTAL1 Input Capacitance XTAL2 Output Capacitance 0.8 3.5 18 18 0.4 2.5 18 18 MCU CLOCK RATE 16 16 MHz max 2.4 2.6 V min V typ V min V typ VDD = 4.5 V to 5.
PAGE 6
ADuC831 SPECIFICATIONS (continued) Parameter POWER REQUIREMENTS Power Supply Voltages AVDD/DVDD to AGND VDD = 5 V VDD = 3 V Unit Test Conditions/Comments 2.7 3.3 V min V max V min V max AVDD /DVDD = 3 V nom 19, 20 4.5 5.
PAGE 7
ADuC831 ABSOLUTE MAXIMUM RATINGS* (TA = 25°C unless otherwise noted.) AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V DVDD to DGND, AVDD to AGND . . . . . . . . . –0.3 V to +7 V Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V Analog Inputs to AGND . . . . . . . . . .
PAGE 8
ADuC831 P1.1/ADC1/T2EX P1.2/ADC2 1 P2.5/A13/A21 P1.3/ADC3 3 36 P2.4/A12/A20 AVDD AVDD 4 AGND AGND 6 8 39 P2.7/PWM1/A15/A23 38 P2.6/PWM0/A14/A22 P1.2/ADC2 3 37 P1.3/ADC3 4 AVDD 5 35 DGND ADuC831 52-LEAD PQFP 34 DVDD TOP VIEW (Not to Scale) 33 XTAL2 32 XTAL1 DAC0 9 DAC1 10 31 P2.3/A11/A19 AGND CREF 30 P2.2/A10/A18 VREF P1.4/ADC4 11 29 P2.1/A9/A17 P1.5/ADC5/SS 12 P1.6/ADC6 13 28 27 ADC CONTROL AND CALIBRATION DAC CONTROL MCU CORE ALE PSEN 44 43 EA P0.
PAGE 9
ADuC831 PIN FUNCTION DESCRIPTIONS Mnemonic Type Function DVDD AVDD CREF VREF P P I I/O AGND P1.0–P1.7 G I ADC0–ADC7 T2 I I T2EX I SS SDATA SCLOCK MOSI MISO DAC0 DAC1 RESET P3.0–P3.7 I I/O I/O I/O I/O O O I I/O PWMC PWM0 PWM1 RxD TxD INT0 I O O I/O O I INT1 I T0 T1 CONVST I I I WR RD XTAL2 XTAL1 DGND P2.0–P2.7 (A8–A15) (A16–A23) O O O I G I/O REV.
PAGE 10
ADuC831 PIN FUNCTION DESCRIPTIONS (continued) Mnemonic Type Function PSEN O ALE O EA I P0.7–P0.0 (A0–A7) I/O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution.
PAGE 11
Typical Performance Characteristics–ADuC831 The typical performance plots presented in this section illustrate typical performance of the ADuC831 under various operating conditions. TPC 1 and TPC 2 below show typical ADC Integral Nonlinearity (INL) errors from ADC code 0 to code 4095 at 5 V and 3 V supplies respectively. The ADC is using its internal reference (2.5 V) and operating at a sampling rate of 152 kHz and the typically worst-case errors in both plots is just less than 0.3 LSBs.
PAGE 12
ADuC831 1.0 0.7 0.7 AV DD /DVDD = 3V AV DD /DVDD = 5V fS = 152kHz 0.8 fS = 152kHz 0.5 0.5 0.6 WCP–DNL – LSBs LSBs 0.2 0 –0.2 –0.4 0.3 0.3 0.1 0.1 –0.1 –0.1 WCN DNL –0.3 –0.3 –0.5 –0.5 WCN–DNL – LSBs WCP DNL 0.4 –0.6 –0.8 –0.7 –0.7 –1.0 0 511 1023 1535 2047 2559 ADC CODES 3071 3583 0.5 4095 TPC 5. Typical DNL Error, VDD = 5 V 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE – V 3.0 TPC 8. Typical Worst Case DNL Error vs. VREF, VDD = 3 V 10000 1.0 AV DD /DVDD = 3V fS = 152kHz 0.
PAGE 13
ADuC831 80 20 –20 –80 70 –60 dBs –75 SNR SNR – dBs –40 fS = 152kHz 75 –80 –100 THD 65 –85 60 –90 55 –95 THD – dBs 0 –70 AV DD /DVDD = 3V AVDD / DVDD = 5V fS = 152kHz fIN = 9.910kHz SNR = 71.3dB THD = –88.0dB ENOB = 11.6 –120 –140 –160 –100 50 0 10 20 30 40 50 60 70 0.5 FREQUENCY – kHz TPC 11. Dynamic Performance at VDD = 5 V 80 AVDD / DVDD = 3V fS = 149.79kHz fIN = 9.910kHz SNR = 71.0dB THD = –83.0dB ENOB = 11.
PAGE 14
ADuC831 MEMORY ORGANIZATION 7FH The ADuC831 contains four different memory blocks: • 62 kBytes of On-Chip Flash/EE Program Memory • 4 kBytes of On-Chip Flash/EE Data Memory • 256 Bytes of General-Purpose RAM • 2 kBytes of Internal XRAM GENERAL-PURPOSE AREA 30H 2FH BANKS BIT-ADDRESSABLE (BIT ADDRESSES) SELECTED Flash/EE Program Memory VIA The ADuC831 provides 62 kBytes of Flash/EE program memory to run user code.
PAGE 15
ADuC831 External Data Memory (External XRAM) Just like a standard 8051 compatible core, the ADuC831 can access external data memory using a MOVX instruction. The MOVX instruction automatically outputs the various control strobes required to access the data memory. 4-kBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH/EE DATA MEMORY 62-kBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH/EE PROGRAM MEMORY The ADuC831, however, can access up to 16 MBytes of external data memory.
PAGE 16
ADuC831 Data Pointer (DPTR) The Data Pointer is made up of three 8-bit registers, named DPP (page byte), DPH (high byte) and DPL (low byte). These are used to provide memory addresses for internal and external code access and external data access. It may be manipulated as a 16-bit register (DPTR = DPH, DPL), although INC DPTR instructions will automatically carry over to DPP, or as three independent 8-bit registers (DPP, DPH, DPL). The ADuC831 supports dual data pointers.
PAGE 17
ADuC831 figure below (NOT USED). Unoccupied locations in the SFR address space are not implemented, i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is returned. SFR locations reserved for on-chip testing are shown lighter shaded below (RESERVED) and should not be accessed by user software. Sixteen of the SFR locations are also bit addressable and denoted by '1' in the figure below, i.e., the bit addressable SFRs are those whose address ends in 0H or 8H.
PAGE 18
ADuC831 ADC CIRCUIT INFORMATION General Overview ADC Transfer Function The ADC conversion block incorporates a fast, 8-channel, 12-bit, single supply ADC. This block provides the user with multichannel mux, track/hold, on-chip reference, calibration features, and ADC. All components in this block are easily configured via a 3-register SFR interface. The ADC consists of a conventional successive-approximation converter based around a capacitor DAC. The converter accepts an analog input range of 0 to VREF.
PAGE 19
ADuC831 ADCCON1 – (ADC Control SFR #1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as detailed below. SFR Address: EFH SFR Power-On Default Value: 00H Bit Addressable: NO Table III. ADCCON1 SFR Bit Designations Bit Name Description ADCCON1.7 MD1 ADCCON1.6 EXT_REF ADCCON1.5 ADCCON1.4 CK1 CK0 The Mode bit selects the active operating mode of the ADC. Set by the user to power up the ADC. Cleared by the user to power down the ADC.
PAGE 20
ADuC831 ADCCON2 – (ADC Control SFR #2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address: SFR Power-On Default Value: Bit Addressable: D8H 00H YES Table IV. ADCCON2 SFR Bit Designations Bit Name ADCCON2.7 ADCI ADCCON2.6 DMA ADCCON2.5 CCONV ADCCON2.4 SCONV ADCCON2.3 ADCCON2.2 ADCCON2.1 ADCCON2.
PAGE 21
ADuC831 ADCCON3 – (ADC Control SFR #3) The ADCCON3 register controls the operation of various calibration modes as well as giving an indication of ADC busy status. SFR Address: SFR Power-On Default Value: Bit Addressable: F5H 00H NO Table V. ADCCON3 SFR Bit Designations Bit Name ADCCON3.7 BUSY ADCCON3.6 GNCLD ADCCON3.5 AVGS1 ADCCON3.4 AVGS0 ADCCON3.3 RSVD ADCCON3.2 RSVD ADCCON3.1 TYPICAL ADCCON3.0 SCAL REV.
PAGE 22
ADuC831 incoming high-frequency noise, its primary function is to ensure that the transient demands of the ADC input stage are met. It Driving the A/D Converter The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. Figure 9 shows the equivalent circuit of the analog input section. Each ADC conversion is divided into two distinct phases as defined by the position of the switches in Figure 9.
PAGE 23
ADuC831 Keep in mind that the ADC’s transfer function is 0 to VREF, and any signal range lost to amplifier saturation near ground will impact dynamic range. Though the op amps in Table VI are capable of delivering output signals very closely approaching ground, no amplifier can deliver signals all the way to ground when powered by a single supply. Therefore, if a negative supply is available, you might consider using it to power the front end amplifiers.
PAGE 24
ADuC831 3. The external memory must be preconfigured. This consists of writing the required ADC channel IDs into the top four bits of every second memory location in the external SRAM starting at the first address specified by the DMA address pointer. As the ADC DMA mode operates independent from the ADuC831 core, it is necessary to provide it with a stop command. This is done by duplicating the last channel ID to be converted followed by “1111” into the next channel selection field.
PAGE 25
ADuC831 The DMA logic operates from the ADC clock and uses pipelining to perform the ADC conversions and access the external memory at the same time. The time it takes to perform one ADC conversion is called a DMA cycle. The actions performed by the logic during a typical DMA cycle are shown in the following diagram. ADC Offset and Gain Calibration Coefficients The ADuC831 has two ADC calibration coefficients, one for offset calibration and one for gain calibration.
PAGE 26
ADuC831 INITIATING CALIBRATION IN CODE When calibrating the ADC, using ADCCON1 the ADC should be set up into the configuration in which it will be used. The ADCCON3 register can then be used to set the device up and calibrate the ADC offset and gain.
PAGE 27
ADuC831 NONVOLATILE FLASH/EE MEMORY Flash/EE Memory Overview The ADuC831 incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable code, and data memory space. Flash/EE memory is a relatively recent type of nonvolatile memory technology and is based on a single transistor cell architecture. This technology is basically an outgrowth of EPROM technology and was developed through the late 1980s.
PAGE 28
ADuC831 after Reset.” If using a bootloader, this option is recommended to ensure that the bootloader always executes the correct code after reset. Using the Flash/EE Program Memory The 62 kByte Flash/EE program memory array is mapped into the lower 62 kBytes of the 64 kBytes program space addressable by the ADuC831, and is used to hold user code in typical applications.
PAGE 29
ADuC831 A block diagram of the SFR interface to the Flash/EE data memory array is shown in Figure 20.
PAGE 30
ADuC831 Example: Programming the Flash/EE Data Memory Flash/EE Memory Timing A user wishes to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other three bytes already in this page.
PAGE 31
ADuC831 ADuC831 Configuration SFR (CFG831) The CFG831 SFR contains the necessary bits to configure the internal XRAM, EPROM controller, PWM output selection and frequency, DAC buffer, and the extended SP. By default it configures the user into 8051 mode, i.e., extended SP is disabled, internal XRAM is disabled. CFG831 SFR Address Power-On Default Value Bit Addressable ADuC831 Config SFR AFH 10*H No Table VIII.
PAGE 32
ADuC831 USER INTERFACE TO OTHER ON-CHIP ADuC831 PERIPHERALS The following section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC831 incorporates two 12-bit, voltage output DACs on-chip. Each has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. Each has two selectable ranges, 0 V to VREF (the internal band gap 2.5 V reference) and 0 V to AVDD.
PAGE 33
ADuC831 VDD Using the DAC The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 21. Details of the actual DAC architecture can be found in U.S. Patent Number 5969657 (www.uspto.gov). Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity.
PAGE 34
ADuC831 3 To drive significant loads with the DAC outputs, external buffering may be required (even with the internal buffer enabled), as illustrated in Figure 25. A list of recommended op-amps is in Table VI. OUTPUT VOLTAGE – V DAC LOADED WITH 0FFFH 2 DAC0 1 ADuC831 DAC LOADED WITH 0000H 0 0 5 10 SOURCE/SINK CURRENT – mA DAC1 15 Figure 25. Buffering the DAC Outputs Figure 24.
PAGE 35
ADuC831 PULSEWIDTH MODULATOR (PWM) The PWM on the ADuC831 is highly flexible PWM offering programmable resolution and input clock, and can be configured for any one of six different modes of operation. Two of these modes allow the PWM to be configured as a - DAC with up to 16 bits of resolution. A block diagram of the PWM is shown in Figure 26. fOSC T0/ EXTERNAL PWM CLOCK fOSC /DIVIDE FACTOR/15 CLOCK SELECT PROGRAMMABLE DIVIDER fOSC /DIVIDE FACTOR 16-BIT PWM COUNTER P2.6 COMPARE P2.
PAGE 36
ADuC831 PWM1L PWM MODES OF OPERATION MODE 0: PWM Disabled PWM COUNTER The PWM is disabled, allowing P2.6 and P2.7 to be used as normal. PWM0L MODE 1: Single Variable Resolution PWM PWM1H PWM0H In Mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the PWM to be variable. 0 P2.6 PWM1H/L sets the period of the output waveform. Reducing PWM1H/L reduces the resolution of the PWM output but increases the maximum output rate of the PWM.
PAGE 37
ADuC831 MODE 4: Dual NRZ 16-Bit - DAC PWM1L PWM COUNTERS Mode 4 provides a high speed PWM output similar to that of a - DAC. Typically, this mode will be used with the PWM clock equal to 16 MHz. PWM1H PWM0L In this mode P2.6 and P2.7 are updated every PWM clock (62 ns in the case of 16 MHz). Over any 65536 cycles (16 bit PWM) PWM0 (P2.6) is high for PWM0H/L cycles and low for (65536 - PWM0H/L) cycles. Similarly PWM1 (P2.7) is high for PWM1H/L cycles and low for (65536 - PWM1H/L) cycles.
PAGE 38
ADuC831 SERIAL PERIPHERAL INTERFACE The ADuC831 integrates a complete hardware Serial Peripheral Interface (SPI) on-chip. SPI is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. It should be noted that the SPI pins are shared with the I2C interface pins. Therefore, the user can only enable one or the other interface at any given time (see SPE in Table XI below).
PAGE 39
ADuC831 SPIDAT SPI Data Register Function The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. F7H 00H No SFR Address Power-On Default Value Bit Addressable Using the SPI Interface SPI Interface—Master Mode Depending on the configuration of the bits in the SPICON SFR shown in Table XI, the ADuC831 SPI interface will transmit or receive data in a number of possible modes.
PAGE 40
ADuC831 I2C COMPATIBLE INTERFACE The ADuC831 supports a fully licensed* I2C serial interface. The I2C interface is implemented as a full hardware slave and software master. SDATA is the data I/O pin and SCLOCK is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface. Therefore, the user can only enable one or the other interface at any given time (see SPE in SPICON previously).
PAGE 41
ADuC831 The main features of the MicroConverter I2C interface are: • Only two bus lines are required; a serial data line (SDATA) and a serial clock line (SCLOCK). • An I2C master can communicate with multiple slave devices. Because each slave device has a unique 7-bit address, single master/slave relationships can exist at all times even in a multislave environment (Figure 34). Once enabled in I2C slave mode the slave controller waits for a START condition.
PAGE 42
ADuC831 DUAL DATA POINTER The ADuC831 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON also includes some nice features such as automatic hardware post-increment and post-decrement as well as automatic data pointer toggle. DPCON is described in Table XIII. DPCON SFR Address Power-On Default Value Bit Addressable Data Pointer Control SFR A7H 00H No Table XIII.
PAGE 43
ADuC831 POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors the DVDD supply on the ADuC831. It will indicate when any of the supply pins drops below one of four userselectable voltage trip points, from 4.63 V to 4.39 V. For correct operation of the Power Supply Monitor function, AVDD must be equal to or greater than 2.7 V. Monitor function is controlled via the PSMCON SFR.
PAGE 44
ADuC831 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC831 enters an erroneous state, possibly due to a programming error or electrical noise. The watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR.
PAGE 45
ADuC831 TCEN TIME INTERVAL COUNTER (TIC) A time interval counter is provided on-chip for counting longer intervals than the standard 8051 compatible timers are capable of. The TIC is capable of timeout intervals ranging from 1/128 second to 255 hours. Furthermore, this counter is clocked by an internal R/C oscillator rather than the external crystal and has the ability to remain active in power-down mode and time long power-down intervals.
PAGE 46
ADuC831 INTVAL User Time Interval Select Register Function SFR Address Power-On Default Value Bit Addressable Valid Value User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled.
PAGE 47
ADuC831 8052 COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. These remaining functions are mostly 8052 compatible (with a few additional features) and are controlled via standard 8052 SFR bit definitions. Parallel I/O The ADuC831 uses four input/output ports to exchange data with external devices.
PAGE 48
ADuC831 In general-purpose I/O port mode, Port 2 pins that have 1s written to them are pulled high by the internal pull-ups (Figure 39) and, in that state, they can be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 pins with 0s written to them will drive a logic low output voltage (VOL) and will be capable of sinking 1.6 mA. DVDD READ LATCH INTERNAL BUS WRITE TO LATCH P2.6 and P2.7 can also be used as PWM outputs.
PAGE 49
ADuC831 DVDD SPE = 0 (I2C ENABLE) HARDWARE I2C (SLAVE ONLY) SFR BITS Read-Modify-Write Instructions Some 8051 instructions that read a port read the latch, and others read the pin. The instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and then rewrite it to the latch. These are called “read-modifywrite” instructions. Listed below are the read-modify-write instructions.
PAGE 50
ADuC831 In “Counter” function, the TLx register is incremented by a 1-to-0 transition at its corresponding external input pin, T0, T1, or T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected.
PAGE 51
ADuC831 TCON Timer/Counter 0 and 1 Control Register SFR Address Power-On Default Value Bit Addressable 88H 00H Yes Table XX. TCON SFR Bit Designations Bit Name Description 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1* 2 IT1* 1 IE0* 0 IT0* Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine. Timer 1 Run Control Bit. Set by user to turn on Timer/Counter 1.
PAGE 52
ADuC831 TIMER/COUNTER 0 AND 1 OPERATING MODES Mode 2 (8-Bit Timer/Counter with Autoreload) The following paragraphs describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for Timer 0 as for Timer 1. Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 47.
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ADuC831 T2CON Timer/Counter 2 Control Register SFR Address Power-On Default Value Bit Addressable C8H 00H Yes Table XXI. T2CON SFR Bit Designations Bit Name Description 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 CNT2 0 CAP2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 will not be set when either RCLK = 1 or TCLK = 1. Cleared by user software. Timer 2 External Flag.
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ADuC831 Timer/Counter Operation Modes 16-Bit Capture Mode The following paragraphs describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XXII. In the Capture mode, there are again two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter which, upon overflowing, sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt.
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ADuC831 UART SERIAL INTERFACE The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, the first byte will be lost. The physical interface to the serial data network is via pins RXD(P3.0) and TXD(P3.
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ADuC831 Mode 0: 8-Bit Shift Register Mode Mode 2: 9-Bit UART with Fixed Baud Rate Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. The data is shifted out of the RxD line. The eight bits are transmitted with the least-significant bit (LSB) first, as shown in Figure 51.
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ADuC831 Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Modes 1 and 3 Baud Rate = ( 2SMOD / 32 ) × (Timer 1 Overflow Rate) The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either timer or counter operation, and in any of its three running modes.
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ADuC831 Timer 3 Generated Baud Rates The high integer dividers in a UART block mean that high speed baud rates are not always possible using some particular crystals. For example, using a 12 MHz crystal, a baud rate of 115200 is not possible. To address this problem, the ADuC831 has added a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates.
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ADuC831 INTERRUPT SYSTEM The ADuC831 provides a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs. IE IP IEIP2 Interrupt Enable Register Interrupt Priority Register Secondary Interrupt Enable Register IE Interrupt Enable Register SFR Address Power-On Default Value Bit Addressable A8H 00H Yes Table XXVIII.
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ADuC831 Interrupt Priority ADuC831 HARDWARE DESIGN CONSIDERATIONS The Interrupt Enable registers are written by the user to enable individual interrupt sources, while the Interrupt Priority registers allow the user to select one of two priority levels for each interrupt. An interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt will be serviced first.
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ADuC831 (Ports 0 and 2) are dedicated to bus functions during external program memory fetches. Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the program counter (PCL) as an address, and then goes into a float state awaiting the arrival of the code byte from the program memory. During the time that the low byte of the program counter is valid on P0, the signal ALE (Address Latch Enable) clocks this byte into an address latch.
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ADuC831 As an alternative to providing two separate power supplies, the user can help keep AVDD quiet by placing a small series resistor and/or ferrite bead between it and DVDD, and then decoupling AVDD separately to ground. An example of this configuration is shown in Figure 61. With this configuration other analog circuitry (such as op amps, voltage reference, and so on) can be powered from the AVDD supply line as well.
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ADuC831 2.45V TYP DVDD 1.0V TYP 128ms TYP 128ms TYP 1.0V TYP a. PLACE ANALOG COMPONENTS HERE PLACE DIGITAL COMPONENTS HERE AGND INTERNAL CORE RESET DGND Figure 62. Internal POR Operation Grounding and Board Layout Recommendations As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC831-based designs in order to achieve optimum performance from the ADC and DACs. b.
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ADuC831 DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) DVDD 1k DVDD ANALOG INPUT 48 47 46 45 44 43 42 41 40 EA 49 PSEN 50 DVDD 51 52 ADC0 DGND 1k 2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN) 39 38 37 AVDD DVDD 36 AVDD DGND 35 AGND VREF OUTPUT DVDD 34 ADuC831 CREF XTAL2 33 VREF XTAL1 32 DAC0 31 DAC1 30 DAC OUTPUT 11.
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ADuC831 DEVELOPMENT TOOLS Download—In-Circuit Serial Downloader There are two models of development tools available for the ADuC831, namely: QuickStart—Entry-level development system QuickStart Plus—Comprehensive development system These systems are described briefly below. The Serial Downloader is a Windows application that allows the user to serially download an assembled program (Intel Hex format file) to the on-chip program FLASH memory via the serial COM1 port on a standard PC.
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ADuC831 TIMING SPECIFICATIONS1, 2, 3 (AV DD = DVDD = 3.0 V or 5.0 V 10%. All specifications TA = TMIN to TMAX, unless otherwise noted.) Parameter Min CLOCK INPUT (External Clock Driven XTAL1) XTAL1 Period tCK tCKL XTAL1 Width Low XTAL1 Width High tCKH XTAL1 Rise Time tCKR tCKF XTAL1 Fall Time tCYC4 ADuC831 Machine Cycle Time 12 MHz Typ Max 83.33 Variable Clock Min Typ Max 62.
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ADuC831 Parameter 12 MHz Min Max Variable Clock Min Max 127 43 53 2tCK – 40 tCK – 40 tCK – 30 Unit Figure ns ns ns ns ns ns ns ns ns ns ns ns 70 70 70 70 70 70 70 70 70 70 70 70 EXTERNAL PROGRAM MEMORY READ CYCLE tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tPHAX ALE Pulsewidth Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulsewidth PSEN Low to Valid Instruction In Input Instruction Hold after PSEN Input Instructi
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ADuC831 Parameter 12 MHz Min Max Variable Clock Min Max 400 43 48 6tCK – 100 tCK – 40 tCK – 35 Unit Figure ns ns ns ns ns ns ns ns ns ns ns ns 71 71 71 71 71 71 71 71 71 71 71 71 EXTERNAL DATA MEMORY READ CYCLE tRLRH tAVLL tLLAX tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tRLAZ tWHLH RD Pulsewidth Address Valid after ALE Low Address Hold after ALE Low RD Low to Valid Data In Data and Address Hold after RD Data Float after RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low A
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ADuC831 Parameter 12 MHz Min Max Variable Clock Min Max Unit Figure 400 43 48 200 203 33 433 33 43 6tCK – 100 tCK – 40 tCK – 35 3tCK – 50 4tCK – 130 tCK – 50 7tCK – 150 tCK – 50 tCK – 40 ns ns ns ns ns ns ns ns ns 72 72 72 72 72 72 72 72 72 EXTERNAL DATA MEMORY WRITE CYCLE tWLWH tAVLL tLLAX tLLWL tAVWL tQVWX tQVWH tWHQX tWHLH WR Pulsewidth Address Valid after ALE Low Address Hold after ALE Low ALE Low to RD or WR Low Address Valid to RD or WR Low Data Valid to WR Transition Data Setup before WR Da
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ADuC831 Parameter Min 12 MHz Typ Max Variable Clock Typ Max Min Unit Figure µs ns ns ns ns 73 73 73 73 73 UART TIMING (Shift Register Mode) tXLXL tQVXH tDVXH tXHDX tXHQX Serial Port Clock Cycle Time Output Data Setup to Clock Input Data Setup to Clock Input Data Hold after Clock Output Data Hold after Clock 1.
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ADuC831 Parameter Min Max Unit Figure µs µs µs µs µs µs µs µs 74 74 74 74 74 74 74 74 ns ns ns 74 74 74 2 I C COMPATIBLE INTERFACE TIMING SCLOCK Low Pulsewidth tL tH SCLOCK High Pulsewidth Start Condition Hold Time tSHD Data Setup Time tDSU Data Hold Time tDHD tRSU Setup Time for Repeated Start Stop Condition Setup Time tPSU Bus Free Time Between a STOP tBUF Condition and a START Condition Rise Time of Both SCLOCK and SDATA tR Fall Time of Both SCLOCK and SDATA tF tSUP* Pulsewidth of Spike Suppres
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ADuC831 Parameter Min Typ Max Unit Figure ns ns ns ns ns ns ns ns ns 75 75 75 75 75 75 75 75 75 SPI MASTER MODE TIMING (CPHA = 1) tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time SCLOCK (CPOL = 0) tSH 330 330 50 100 100 10 10 10 10 25 25 25 25 tSL tSR SCLOCK (CPOL = 1
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ADuC831 Parameter Min Typ Max Unit Figure ns ns ns ns ns ns ns ns ns ns 76 76 76 76 76 76 76 76 76 76 SPI MASTER MODE TIMING (CPHA = 0) tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge Data Output Setup before SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time SCLOCK (CPOL = 0) tSH 330 330 50 150 100 10
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ADuC831 Parameter Min Typ Max Unit Figure ns ns ns ns ns ns ns ns ns ns ns 77 77 77 77 77 77 77 77 77 77 77 SPI SLAVE MODE TIMING (CPHA = 1) tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS SS to SCLOCK Edge SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time SS High after SCLOCK Edge 0 330 330 50 100 100 10 10 10
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ADuC831 Parameter Min Typ Max Unit Figure ns ns ns ns ns ns ns ns ns ns ns ns 78 78 78 78 78 78 78 78 78 78 78 78 SPI SLAVE MODE TIMING (CPHA = 0) tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOSS tSFS SS to SCLOCK Edge SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time Data Output Valid after SS Edge SS High after
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ADuC831 OUTLINE DIMENSIONS 52-Lead Plastic Quad Flatpack [MQFP] (S-52) Dimensions shown in millimeters 14.15 13.90 SQ 13.65 2.45 MAX 39 27 40 SEATING PLANE C02986–0–11/02(0) 1.03 0.88 0.73 26 7.80 REF 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) VIEW A PIN 1 52 14 1 0.23 0.11 13 0.65 BSC 0.38 0.22 2.10 2.00 1.95 7 0 0.