Datasheet

REV. B
ADuC824
–46–
WDCON Watchdog Timer Control Register
SFR Address C0H
Power-On Default Value 10H
Bit Addressable Yes
3ERP2ERP1ERP0ERPRIDWSDWEDWRWDW
Table XVII. WDCON SFR Bit Designations
Bit Name Description
7 PRE3 Watchdog Timer Prescale Bits
6 PRE2 The Watchdog timeout period is given by the equation: t
WD
= (2
PRE
× (2
9
/f
PLL
))
5 PRE1 (0 ≤ PRE ≤ 7; f
PLL
= 32.768 kHz)
4 PRE0 PRE3 PRE2 PRE1 PRE0Timout Period (ms) Action
0 0 0 0 15.6 Reset or Interrupt
0 0 0 1 31.2 Reset or Interrupt
0 0 1 0 62.5 Reset or Interrupt
0 0 1 1 125 Reset or Interrupt
0 1 0 0 250 Reset or Interrupt
0 1 0 1 500 Reset or Interrupt
0 1 1 0 1000 Reset or Interrupt
0 1 1 1 2000 Reset or Interrupt
1 0 0 0 0.0 Immediate Reset
PRE3–0 > 1001 Reserved
3 WDIR Watchdog Interrupt Response Enable Bit
If this bit is set by the user, the watchdog will generate an interrupt response instead of a system
reset when the watchdog timeout period has expired. This interrupt is not disabled by the CLR
EA instruction and it is also a fixed, high-priority interrupt. If the watchdog is not being used to
monitor the system, it can alternatively be used as a timer. The prescaler is used to set the timeout
period in which an interrupt will be generated. (See also Note 1, Table XXXIV in the Interrupt
System section.)
2 WDS Watchdog Status Bit
Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.
Cleared by writing a ‘0’ or by an external hardware reset. It is not cleared by a watchdog reset.
1 WDE Watchdog Enable Bit
Set by user to enable the watchdog and clear its counters. If this bit is not set by the user within
the watchdog timeout period, the watchdog will generate a reset or interrupt, depending on WDIR.
Cleared under the following conditions, User writes ‘0,’ Watchdog Reset (WDIR = ‘0’); Hardware
Reset; PSM Interrupt.
0 WDWR Watchdog Write Enable Bit
To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must
be set and the very next instruction must be a write instruction to the WDCON SFR.
e.g., CLR EA ; disable interrupts while writing
to WDT
SETB WDWR ; allow write to WDCON
MOV WDCON, #72h ; enable WDT for 2.0s timeout
SET B EA ; enable interrupts again (if rqd)
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset or
interrupt within a reasonable amount of time if the ADuC824
enters an erroneous state, possibly due to a programming error,
electrical noise, or RFI. The Watchdog function can be disabled by
clearing the WDE (Watchdog Enable) bit in the Watchdog Control
(WDCON) SFR. When enabled; the watchdog circuit will generate
a system reset or interrupt (WDS) if the user program fails to set
the watchdog (WDE) bit within a predetermined amount of time
(see PRE3–0 bits in WDCON). The watchdog timer itself is a
16-bit counter that is clocked at 32.768 kHz. The watchdog
time-out interval can be adjusted via the PRE3–0 bits in WDCON.
Full Control and Status of the watchdog timer function can be
controlled via the watchdog timer control SFR (WDCON). The
WDCON SFR can only be written by user software if the double
write sequence described in WDWR below is initiated on every
write access to the WDCON SFR.