Datasheet

REV. B
ADuC824
–30–
OF0H/OF0M/OF0L (Primary ADC Offset Calibration Registers*)
These three 8-bit registers hold the 24-bit offset calibration coefficient for the Primary ADC. These registers are configured at power-
on with a factory default value of 800000Hex. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration is initiated by the user via MD2–0 bits in the ADCMODE register.
SFR Address OF0H Primary ADC Offset Coefficient High Byte E3H
OF0M Primary ADC Offset Coefficient Middle Byte E2H
OF0L Primary ADC Offset Coefficient Low Byte E1H
Power-On Default Value 800000H OF0H, OF0M, and OF0L, Respectively
Bit Addressable No All Three Registers
OF1H/OF1L (Auxiliary ADC Offset Calibration Registers*)
These two 8-bit registers hold the 16-bit offset calibration coefficient for the Auxiliary ADC. These registers are configured at power-on
with a factory default value of 8000Hex. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration is initiated by the user via the MD2–0 bits in the ADCMODE register.
SFR Address OF1H Auxiliary ADC Offset Coefficient High Byte E5H
OF1L Auxiliary ADC Offset Coefficient Low Byte E4H
Power-On Default Value 8000H OF1H and OF1L Respectively
Bit Addressable No Both Registers
GN0H/GN0M/GN0L (Primary ADC Gain Calibration Registers*)
These three 8-bit registers hold the 24-bit gain calibration coefficient for the Primary ADC. These registers are configured at power-on
with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these
bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0 bits in the
ADCMODE register.
SFR Address GN0H Primary ADC Gain Coefficient High Byte EBH
GN0M Primary ADC Gain Coefficient Middle Byte EAH
GN0L Primary ADC Gain Coefficient Low Byte E9H
Power-On Default Value Configured at factory final test, see notes above.
Bit Addressable No All Three Registers
GN1H/GN1L (Auxiliary ADC Gain Calibration Registers*)
These two 8-bit registers hold the 16-bit gain calibration coefficient for the Auxiliary ADC. These registers are configured at power-on
with a factory calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these
bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0 bits in the
ADCMODE register.
SFR Address GN1H Auxiliary ADC Gain Coefficient High Byte EDH
GN1L Auxiliary ADC Gain Coefficient Low Byte ECH
Power-On Default Value Configured at factory final test, see notes above.
Bit Addressable No Both Registers
*These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero.