Datasheet

REV. 0
ADuC816
–8–
TIMING SPECIFICATIONS
1, 2, 3
(AV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V; all
specifications T
MIN
to T
MAX
unless otherwise noted.)
32.768 kHz External Crystal
Parameter Min Typ Max Unit Figure
CLOCK INPUT (External Clock Driven XTAL1)
t
CK
XTAL1 Period 30.52 μs1
t
CKL
XTAL1 Width Low 15.16 μs1
t
CKH
XTAL1 Width High 15.16 μs1
t
CKR
XTAL1 Rise Time 20 ns 1
t
CKF
XTAL1 Fall Time 20 ns 1
1/t
CORE
ADuC816 Core Clock Frequency
4
0.098 12.58 MHz
t
CORE
ADuC816 Core Clock Period
5
0.636 μs
t
CYC
ADuC816 Machine Cycle Time
6
0.95 7.6 122.45 μs
NOTES
1
AC inputs during testing are driven at DV
DD
– 0.5 V for a Logic 1, and 0.45 V for a Logic 0. Timing measurements are made at V
IH
min for a Logic 1, and V
IL
max
for a Logic 0 as shown in Figure 2.
2
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded V
OH
/V
OL
level occurs as shown in Figure 2.
3
C
LOAD
for Port0, ALE, PSEN outputs = 100 pF; C
LOAD
for all other outputs = 80 pF unless otherwise noted.
4
ADuC816 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a Stable 12.583 MHz internal clock for the system.
The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
5
This number is measured at the default Core_Clk operating frequency of 1.57 MHz.
6
ADuC816 Machine Cycle Time is nominally defined as 12/Core_CLK.
Specifications subject to change without notice.
t
CHK
t
CKL
t
CK
t
CKF
t
CKR
Figure 1. XTAL1 Input
DV
DD
– 0.5V
0.45V
0.2DV
DD
+ 0.9V
TEST POINTS
0.2DV
DD
– 0.1V
V
LOAD
– 0.1V
V
LOAD
V
LOAD
+ 0.1V
TIMING
REFERENCE
POINTS
V
LOAD
– 0.1V
V
LOAD
V
LOAD
+ 0.1V
Figure 2. Timing Waveform Characteristics
REV. A