Datasheet

REV. 0
ADuC816
–62–
ADuC816 HARDWARE DESIGN CONSIDERATIONS
This section outlines some of the key hardware design consider-
ations that must be addressed when integrating the ADuC816
into any hardware system.
Clock Oscillator
As described earlier, the core clock frequency for the ADuC816
is generated from an on-chip PLL that locks onto a multiple
(384 times) of 32.768 kHz. The latter is generated from an inter-
nal clock oscillator. To use the internal clock oscillator, connect
a 32.768 kHz parallel resonant crystal between XTAL1 and
XTAL2 pins (32 and 33) as shown in Figure 42.
As shown in the typical external crystal connection diagram in
Figure 42, two internal 12 pF capacitors are provided on-chip.
These are connected internally, directly to the XTAL1 and
XTAL2 pins and the total input capacitances at both pins is
detailed in the specification section of this data sheet. The value
of the total load capacitance required for the external crystal should
be the value recommended by the crystal manufacturer for use
with that specific crystal. In many cases, because of the on-chip
capacitors, additional external load capacitors will not be required.
XTAL2
XTAL1
32.768kHz
TO INTERNAL
PLL
ADuC816
12pF
12pF
Figure 42. External Parallel Resonant Crystal Connections
External Memory Interface
In addition to its internal program and data memories, the
ADuC816 can access up to 64 Kbytes of external program memory
(ROM/PROM/etc.) and up to 16 Mbytes of external data
memory (SRAM).
To select from which code space (internal or external program
memory) to begin executing instructions, tie the EA (external
access) pin high or low, respectively. When EA is high (pulled up
to V
DD
), user program execution will start at address 0 of the
internal 8 Kbytes Flash/EE code space. When EA is low (tied to
ground) user program execution will start at address 0 of the
external code space. In either case, addresses above 1FFF hex
(8K) are mapped to the external space.
Note that a second very important function of the EA pin is
described in the Single Pin Emulation Mode section of this
data sheet.
External program memory (if used) must be connected to the
ADuC816 as illustrated in Figure 43. Note that 16 I/O lines
(Ports 0 and 2) are dedicated to bus functions during external
program memory fetches. Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the program counter
(PCL) as an address, and then goes into a float state awaiting
the arrival of the code byte from the program memory. During the
time that the low byte of the program counter is valid on P0, the
signal ALE (Address Latch Enable) clocks this byte into an
address latch. Meanwhile, Port 2 (P2) emits the high byte of the
program counter (PCH), then PSEN strobes the EPROM and
the code byte is read into the ADuC816.
LATCH
EPROM
OE
A8–A15
A0–A7
D0–D7
(INSTRUCTION)
ADuC816
PSEN
P2
ALE
P0
Figure 43. External Program Memory Interface
Note that program memory addresses are always 16 bits wide, even
in cases where the actual amount of program memory used is less
than 64 Kbytes. External program execution sacrifices two of the
8-bit ports (P0 and P2) to the function of addressing the program
memory. While executing from external program memory, Ports
0 and 2 can be used simultaneously for read/write access to exter-
nal data memory, but not for general-purpose I/O.
Though both external program memory and external data memory
are accessed by some of the same pins, the two are completely
independent of each other from a software point of view. For
example, the chip can read/write external data memory while
executing from external program memory.
Figure 44 shows a hardware configuration for accessing up to
64 Kbytes of external RAM. This interface is standard to any 8051
compatible MCU.
LATCH
SRAM
OE
A8–A15
A0–A7
D0–D7
(DATA)
ADuC816
RD
P2
ALE
P0
WE
WR
Figure 44. External Data Memory Interface (64 K Address
Space)
If access to more than 64 Kbytes of RAM is desired, a feature
unique to the ADuC816 allows addressing up to 16 Mbytes
of external RAM simply by adding an additional latch as illustrated
in Figure 45.
REV. A