Datasheet

REV. 0
ADuC816
–41–
USER INTERFACE TO OTHER ON-CHIP ADuC816
PERIPHERALS
The following section gives a brief overview of the various
peripherals also available on-chip. A summary of the SFRs used
to control and configure these peripherals is also given.
DAC
The ADuC816 incorporates a 12-bit, voltage output DAC
on-chip. It has a rail-to-rail voltage output buffer capable of
driving 10 kΩ/100 pF. It has two selectable ranges, 0 V to V
REF
(the internal bandgap 2.5 V reference) and 0 V to AV
DD
. It can
operate in 12-bit or 8-bit mode. The DAC has a control regis-
ter, DACCON, and two data registers, DACH/L. The DAC
output can be programmed to appear at Pin 3 or Pin 12. It
should be noted that in 12-bit mode, the DAC voltage output
will be updated as soon as the DACL data SFR has been writ-
ten; therefore, the DAC data registers should be updated as
DACH first followed by DACL.5
DACCON DAC Control Register
SFR Address FDH
Power-On Default Value 00H
Bit Addressable No
---------NIPCAD8CADNRCAD
RLCCAD
NECAD
Table XIV. DACCON SFR Bit Designations
Bit Name Description
7 --- Reserved for Future Use.
6 --- Reserved for Future Use.
5 --- Reserved for Future Use.
4 DACPIN DAC Output Pin Select.
Set by the user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC).
Cleared by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1).
3 DAC8 DAC 8-bit Mode Bit.
Set by user to enable 8-bit DAC operation. In this mode the 8-bits in DACL SFR are routed to
the 8 MSBs of the DAC and the 4 LSBs of the DAC are set to zero.
Cleared by user to operate the DAC in its normal 12-bit mode of operation.
2 DACRN DAC Output Range Bit.
Set by user to configure DAC range of 0 – AV
DD
.
Cleared by user to configure DAC range of 0 – 2.5 V.
1 DACCLR DAC Clear Bit.
Set to “1” by user to enable normal DAC operation.
Cleared to “0” by user to reset DAC data registers DACl/H to zero.
0 DACEN DAC Enable Bit.
Set to “1” by user to enable normal DAC operation.
Cleared to “0” by user to power-down the DAC.
DACH/L DAC Data Registers
Function DAC Data Registers, written by user to update the DAC output.
SFR Address DACL (DAC Data Low Byte) –>FBH
DACH (DAC Data High Byte) –>FCH
Power-On Default Value 00H –>Both Registers
Bit Addressable No –>Both Registers
The 12-bit DAC data should be written into DACH/L right-justified such that DACL contains the lower eight bits, and the lower
nibble of DACH contains the upper four bits.
REV. A