Datasheet

REV. 0
ADuC816
–28–
ADC1CON (Auxiliary ADC Control Register)
Used to configure the Auxiliary ADC for channel selection, external Ref enable and unipolar or bipolar coding. It should be noted that the
Auxiliary ADC only operates on a fixed input range of ± V
REF
.
SFR Address D3H
Power-On Default Value 00H
Bit Addressable No
---1FERX1HCA0HCA1INU---------
Table VI. ADC1CON SFR Bit Designations
Bit Name Description
7 --- Reserved for Future Use.
6 XREF1 Auxiliary ADC External Reference Bit.
Set by user to enable the Auxiliary ADC to use the external reference via REFIN(+)/REFIN(–).
Cleared by user to enable the Auxiliary ADC to use the internal bandgap reference.
5 ACH1 Auxiliary ADC Channel Selection Bits.
4 ACH0 Written by the user to select the single-ended input pins used to drive the Auxiliary ADC as follows:
ACH1 ACH0 Positive Input Negative Input
0 0 AIN3 AGND
0 1 AIN4 AGND
1 0 Temp Sensor* AGND (Temp. Sensor routed to the ADC input)
1 1 AIN5 AGND
3 UNI1 Auxiliary ADC Unipolar Bit.
Set by user to enable unipolar coding, i.e., zero input will result in 0000 hex output.
Cleared by user to enable bipolar coding, zero input will result in 8000 hex output.
2 --- Reserved for Future Use.
1 --- Reserved for Future Use.
0 --- Reserved for Future Use.
*NOTES
1. When the temperature sensor is selected, user code must select internal reference via XREF1 bit above and clear the UNI1 bit (ADC1CON.3) to select bipolar coding.
2. The temperature sensor is factory calibrated to yield conversion results 8000H at 0 °C.
3. A +1°C change in temperature will result in a +1 LSB change in the ADC1H register ADC conversion result.
SF (Sinc Filter Register)
The number in this register sets the decimation factor and thus
the output update rate for the Primary and Auxiliary ADCs.
This SFR cannot be written by user software while either ADC is
active. The update rate applies to both Primary and Auxiliary
ADCs and is calculated as follows:
f
SF
f
ADC MOD
=· ·
1
3
1
8.
Where: f
ADC
= ADC Output Update Rate
f
MOD
= Modulator Clock Frequency = 32.768 kHz
SF = Decimal Value of SF Register
The allowable range for SF is 0Dhex to FFhex. Examples of SF
values and corresponding conversion update rate (f
ADC
) and con-
version time (t
ADC
) are shown in Table VII, the power-on default
value for the SF register is 45 hex, resulting in a default ADC
update rate of just under 20 Hz. Both ADC inputs are chopped
to minimize offset errors, which means that the settling time for
a single conversion or the time to a first conversion result in
continuous conversion mode is 2 × t
ADC
. As mentioned earlier,
all calibration cycles will be carried out automatically with a
maximum, i.e., FFhex, SF value to ensure optimum calibra-
tion performance. Once a calibration cycle has completed, the
value in the SF register will be that programmed by user software.
Table VII. SF SFR Bit Designations
SF(dec) SF(hex) f
ADC
(Hz) t
ADC
(ms)
13 0D 105.3 9.52
69 45 19.79 50.34
255 FF 5.35 186.77
REV. A