Datasheet

ADuC816
Pin No.
52-Lead
MQFP
Pin No.
56-Lead
CSP Mnemonic Type
1
Description
20, 34, 48 22, 36, 51, DV
DD
S Digital Supply, 3 V or 5 V
21, 35, 47 23, 37, 38, 50 DGND S Digital Ground. Ground reference point for the digital circuitry.
26 SCLOCK I/O Serial Interface Clock for either the I2C or SPI Interface. As an input, this pin is a Schmitt-triggered input,
and a weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be
directly controlled in software as a digital output pin.
27 MOSI/SDATA I/O Serial Data I/O for the I
2
C Interface or Master Output/Slave Input for the SPI Interface. A weak
internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly
controlled in software as a digital output pin.
28–31
36–39
30–33
39–42
P2.0–P2.7
(A8–A15)
(A16–A23)
I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to
them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As
inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up
resistors. Port 2 emits the high order address bytes during fetches from external program
memory and middle and high order address bytes during accesses to the 24-bit external data
memory space.
32 34 XTAL1 I Input to the Crystal Oscillator Inverter
33 35 XTAL2 O Output from the Crystal Oscillator Inverter. (See the ADuC816 Hardware Design Considerations
section for description.)
40 43 EA
I/O External Access Enable, Logic Input. When held high, this input enables the device to fetch code
from internal program memory locations 0000h to F7FFh.When held low, this input enables the
device to fetch all instructions from external program memory. To determine the mode of code
execution, i.e., internal or external, the
EA
pin is sampled at the end of an external RESET assertion
or as part of a device power cycle.
EA
may also be used as an external emulation I/O pin, and
therefore the voltage level at this pin must not be changed during normal mode operation as it
may cause an emulation interrupt that will halt code execution.
41 44 PSEN
O Program Store Enable, Logic Output. This output is a control signal that enables the external
program memory to the bus during external fetch operations. It is active every six oscillator
periods except during external data memory accesses. This pin remains high during internal
program execution.
PSEN
can also be used to enable Serial Download mode when pulled low through
a resistor at the end of an external RESET assertion or as part of a device power cycle.
42 45 ALE O Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for
24-bit data address space accesses) of the address to external memory during external code or
data memory access cycles. It is activated every six oscillator periods except during an external
data memory access. It can be disabled by setting the PCON.4 bit in the PCON SFR.
43–46
49–52
46–49
52–55
P0.0–P0.7
(AD0–AD3)
I/O These pins are part of Port 0, which is an 8-bit, open-drain, bidirectional I/O port. Port 0 pins that
have 1s written to them float and in that state can be used (AD4–AD7)as high impedance inputs.
An external pull-up resistor will be required on P0 outputs to force a valid logic high level
externally. Port 0 is also the multiplexed low order address and data bus during accesses to
external program or data memory. In this application, it uses strong internal pull-ups when
emitting 1s.
1
I = Input, O = Output, S = Supply.
REV. A
–20–