Datasheet

ADuC814
Rev. A | Page 66 of 72
Table 36. SPI Master Mode Timing (CPHA = 1)
Parameter Min Typ Max Unit
t
SL
SCLOCK Low Pulse Width
1
630 ns
t
SH
SCLOCK High Pulse Width
1
630 ns
t
DAV
Data Output Valid after SCLOCK Edge 50 ns
t
DSU
Data Input Setup Time before SCLOCK Edge 100 ns
t
DHD
Data Input Hold Time after SCLOCK Edge 100 ns
t
DF
Data Output Fall Time 10 25 ns
t
DR
Data Output Rise Time 10 25 ns
t
SR
SCLOCK Rise Time 10 25 ns
t
SF
SCLOCK Fall Time 10 25 ns
1
Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.
b. SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0, respectively.
SCLOCK
(CPOL = 0)
SCLOCK
(CPOL = 1)
MOSI
MISO
MSB
LSB
LSB IN
BITS 6–1
BITS 6–1
MSB IN
t
DAV
t
DSU
t
DHD
t
DR
t
DF
t
SH
t
SL
t
SR
t
SF
02748-A-005
Figure 63. SPI Master Mode Timing (CPHA = 1)