Datasheet

ADuC814
Rev. A | Page 65 of 72
Table 35. UART Timing (Shift Register Mode)
16.78 MHz Core_Clk Variable Core_Clk
Parameter
Min Typ Max Min Typ Max
Unit
t
XLXL
Serial Port Clock Cycle Time 715 12 t
CORE
µs
t
QVXH
Output Data Setup to Clock 463 10 t
CORE
–133 ns
t
DVXH
Input Data Setup to Clock 252 2 t
CORE
+133 ns
t
XHDX
Input Data Hold after Clock 0 0 ns
t
XHQX
Output Data Hold after Clock 22 2 t
CORE
–117 ns
SET RI
OR
SET TI
BIT 6
t
XLXL
TxD
(OUTPUT CLOCK)
RxD
(OUTPUT DATA)
RxD
(INPUT DATA)
BIT 1LSB
LSB
BIT 1 BIT 6 MSB
t
XHQX
t
QVXH
t
DVXH
t
XHDX
02748-A-004
Figure 62. UART Timing in Shift Register Mode