Datasheet

ADuC814
Rev. A | Page 64 of 72
TIMING SPECIFICATIONS
1,2,3
Table 34. Clock Input (External Clock Driven XTAL1)
AV
DD
= 2.7 V to 3.3 V or 4.75 V to 5.25 V, DV
DD
= 2.7 V to 3.3 V or 4.75 V to 5.25 V; all specifications T
MIN
to T
MAX
, unless otherwise noted
32.768 kHz External Crystal
Parameter
Min Typ Max
Unit
t
CK
XTAL1 Period 30.52 µs
t
CKL
XTAL1 Width Low 15.16 µs
t
CKH
XTAL1 Width High 15.16 µs
t
CKR
XTAL1 Rise Time 20 ns
t
CKF
XTAL1 Fall Time 20 ns
1/t
CORE
ADuC814 Core Clock Frequency
4
0.131 16.78 MHz
t
CORE
ADuC814 Core Clock Period
5
0.476 µs
t
CYC
ADuC814 Machine Cycle Time
6
0.72 5.7 91.55 µs
1
AC inputs during testing are driven at DV
DD
– 0.5 V for a Logic 1, and at 0.45 V for a Logic 0. Timing measurements are made at V
IH
min for a Logic 1, and at V
IL
max for a
Logic 0 as shown in Figure 61.
2
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded V
OH
/V
OL
level occurs as shown in Figure 61.
3
C
LOAD
for all outputs = 80 pF, unless otherwise noted.
4
ADuC814 internal PLL locks onto a multiple (512 times) the external crystal frequency of 32.768 kHz to provide a stable 16.777216 MHz internal clock for the system.
The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
5
This number is measured at the default Core_Clk operating frequency of 2.09 MHz.
6
ADuC814 Machine Cycle Time is nominally defined as 12/Core_CLK.
t
CKH
t
CKL
t
CK
t
CKF
t
CKR
02748-A-002
Figure 60. XTAL1 Input
DV
DD
– 0.5V
0.45V
0.2DV
DD
+0.9V
TEST POINTS
0.2DV
DD
–0.1V
V
LOAD
– 0.1V
V
LOAD
V
LOAD
+ 0.1V
V
LOAD
– 0.1V
V
LOAD
+ 0.1V
TIMING
REFERENCE
POINT
V
LOAD
02748-A-003
Figure 61. Timing Waveform Characteristics