Datasheet

ADuC814
Rev. A | Page 59 of 72
Interrupt Priority
The interrupt enable registers are written by the user to enable
individual interrupt sources, while the interrupt priority
registers allow the user to select one of two priority levels for
each interrupt. An interrupt of a high priority may interrupt the
service routine of a low priority interrupt, and if two interrupts
of different priority occur at the same time, the higher level
interrupt is serviced first. An interrupt cannot be interrupted by
another interrupt of the same priority level. If two interrupts of
the same priority level occur simultaneously, a polling sequence
is observed as shown in Table 32.
Table 32. Priority within an Interrupt Level
Source Priority Description
PSMI 1 (Highest) Power Supply Monitor Interrupt
WDS 2 Watchdog Interrupt
IE0 3 External Interrupt 0
RDY0/RDY1 4 ADC Interrupt
TF0 5 Timer/Counter 0 Interrupt
IE1 6 External Interrupt 1
TF1 7 Timer/Counter 1 Interrupt
ISPI 8 SPI Interrupt
RI + TI 9 Serial Interrupt
TF2 + EXF2 10 Timer/Counter 2 Interrupt
TII 11 (Lowest) Time Interval Counter Interrupt
Interrupt Vectors
When an interrupt occurs, the program counter is pushed onto
the stack, and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in Table 33.
Table 33. Interrupt Vector Addresses
Source Vector Address
IE0 0003H
TF0 000BH
IE1 0013H
TF1 001BH
RI + TI 0023H
TF2 + EXF2 002BH
RDY0/RDY1 (ADC) 0033H
ISPI 003BH
PSMI 0043H
TII 0053H
WDS (WDIR = 1)
1
005BH
1
The watchdog can be configured to generate an interrupt instead of a reset
when it times out. This is used for logging errors or to examine the internal
status of the microcontroller core to understand, from a software debug point
of view, why a watchdog timeout occurred. The watchdog interrupt is slightly
different from normal interrupts in that its priority level is always set to 1, and
it is not possible to disable the interrupt via the global disable bit (EA) in the IE
SFR. This is done to ensure that the interrupt is always responded to if a
watchdog timeout occurs. The watchdog produces an interrupt only if the
watchdog timeout is greater than zero.