Datasheet

ADuC814
Rev. A | Page 50 of 72
TIMER/COUNTER 0 AND 1 OPERATING MODES
The following paragraphs describe the operating modes for
Timer/Counters 0 and 1. Unless otherwise noted, it should be
assumed that these modes of operation are the same for both
Timer 0 and Timer 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter with a divide-by-32
prescaler. Figure 45 shows Mode 0 operation.
CONTROL
TF0
TL0
(5 BITS)
TL0
(8 BITS)
INTERRUPT
P3.4/T0
GATE
TR0
P3.2/INT0
02748-A-051
CORE
CLK*
÷12
C/T = 1
C/T = 0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL
Figure 45. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag TF0. The overflow flag, TF0, can then be used to
request an interrupt. The counted input is enabled to the timer
when TR0 = 1 and either Gate = 0 or
INT0
= 1.
Setting Gate = 1 allows the timer to be controlled by external
input
INT0
to facilitate pulse width measurements. TR0 is a
control bit in the special function register TCON; Gate is in
TMOD. The 13-bit register consists of all eight bits of TH0 and
the lower five bits of TL0. The upper three bits of TL0 are
indeterminate and should be ignored. Setting the run flag (TR0)
does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. Mode 1 is shown in Figure 46.
CONTROL
TF0
TL0
(8 BITS)
TL0
(8 BITS)
INTERRUPT
P3.4/T0
GATE
TR0
P3.2/INT0
02748-A-052
CORE
CLK*
÷12
C/T = 1
C/T = 0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL
Figure 46. Timer/Counter 0, Mode 1
Mode 2 (8-Bit Timer/Counter with Autoreload)
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload, as shown in Figure 47. Overflow from TL0
not only sets TF0, but also reloads TL0 with the contents of TH0,
which is preset by software. The reload leaves TH0 unchanged.
CONTROL
TF0
TL0
(8 BITS)
RELOAD
TL0
(8 BITS)
INTERRUPT
P3.4/T0
GATE
TR0
P3.2/INT0
02748-A-053
CORE
CLK*
÷12
C/T = 1
C/T = 0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL
Figure 47. Timer/Counter 0, Mode 2
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 48. TL0
uses the Timer 0 control bits: C/T, GATE, TR0,
INT0
, and TF0.
TH0 is locked into a timer function (counting machine cycles)
and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0
controls the Timer 1 interrupt. Mode 3 is provided for applica-
tions requiring an extra 8-bit timer or counter. When Timer 0 is
in Mode 3, Timer 1 can be turned on and off by switching it out
of, and into, its own Mode 3, or can still be used by the serial
interface as a baud rate generator. In fact, it can be used in any
application not requiring an interrupt from Timer 1 itself.
CONTROL
TF0
TL0
(8 BITS)
INTERRUPT
P3.4/T0
GATE
TR0
TF1
INTERRUPT
CORE
CLK/12
TR1
P3.2/INT0
02748-A-054
CORE
CLK*
CORE
CLK/12
÷12
TL0
(8 BITS)
C/T = 1
C/T = 0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL
Figure 48. Timer/Counter 0, Mode 3