Datasheet

ADuC814
Rev. A | Page 39 of 72
TIMECON TIC CONTROL REGISTER
SFR Address A1H
Power-On Default 00H
Bit Addressable No
--- TFH ITS1 ITS0 STI TII TIEN TCEN
Table 14. TIMECON SFR Bit Designations
Bit No. Name Description
7 --- Reserved.
6 TFH Twenty-Four Hour Select Bit.
Set by the user to enable the HOUR counter to count from 0 to 23.
Cleared by the user to enable the HOUR counter to count from 0 to 255.
The time interval counter continues to count after a reset when in hours/min/sec mode. If the part is in 24 hour
mode though, this bit is reset and the part now counts in 255 hour mode. The following code segment can be used
to set the TIC back into 24 hour mode after a RESET event.
MOV A,TIMECON ;Move contents of TIMECON into ACC
RRC A ;Rotate ACC right by 1 place into Carry
JNC NOTSET ;If CARRY bit is ! = 1 jump to NOTSET, else continue with next line
ORL TIMECON,#01000000B
;If CARRY bit = 1 for last line, then logical OR TIMECON with 40H
NOTSE: ;continuation of normal code from here
ITS1 Interval Timebase Selection Bits.
4 ITS0 Written by the user to determine the interval counter update rate.
ITS1 ITS0 Interval Timebase
0 0 1/128 Second
0 1 Seconds
1 0 Minutes
1 1 Hours
3 STI Single Time Interval Bit.
Set by the user to generate a single interval timeout. If set, a timeout clears the TIEN bit.
Cleared by the user to allow the interval counter to be automatically reloaded and start counting again at each
interval timeout.
2 TII TIC Interrupt Bit.
Set when the 8-bit interval counter matches the value in the INTVAL SFR.
Cleared by the user software.
1 TIEN Time Interval Enable Bit.
Set by the user to enable the 8-bit time interval counter.
Cleared by the user to disable and clear the contents of the interval counter.
0 TCEN Time Clock Enable Bit.
Set by the user to enable the time clock to the time interval counters.
Cleared by the user to disable the clock to the time interval counters and clear the time interval SFRs.
The time registers (HTHSEC, SEC, MIN and HOUR) can be written while TCEN is low.