Datasheet
ADuC814
Rev. A | Page 22 of 72
SFR INTERFACE TO ADC BLOCK
The ADC operation is fully controlled via three SFRs: ADCCON1, ADCCON2, and ADCCON3. These three registers control the mode
of operation.
ADCCON1 (ADC CONTROL SFR 1)
The ADCCON1 register controls conversion and acquisition times, hardware conversion modes, and power-down modes as detailed
below.
SFR Address EFH
SFR Power-on Default 00H
Bit Addressable No
MODE EXT_REF CK1 CK0 AQ1 AQ0 T2C EXC
Table 6. ADCCON1 SFR Bit Designations
Bit No. Name Description
7 MODE Mode Bit.
This bit selects the operating mode of the ADC.
Set to 1 by the user to power on the ADC.
Set to 0 by the user to power down the ADC.
6 EXT_REF External Reference Select Bit.
This bit selects which reference the ADC uses when performing a conversion.
Set to 1 by the user to switch in an external reference.
Set to 0 by the user to switch in the on-chip band gap reference.
5 CK1 ADC Clock Divide Bits.
4 CK0
CK1 and CK0 combine to select the divide ratio for the PLL master clock used to generate the ADC clock. To ensure
correct ADC operation, the divider ratio must be chosen to reduce the ADC clock to 4.5 MHz and below. The
divider ratio is selected as follows:
CK1 CK0 PLL Divider
0 0 8
0 1 4
1 0 16
1 1 32
3 AQ1 The ADC Acquisition Time Select Bits.
2 AQ0
AQ1 and AQ0 combine to select the number of ADC clocks required for the input track-and-hold amplifier to
acquire the input signal. The acquisition time is selected as follows:
AQ1 AQ0 No. ADC Clks
0 0 1
0 1 2
1 0 3
1 1 4
1 T2C The Timer2 Conversion Bit.
T2C is set to enable the Timer2 overflow bit to be used as the ADC convert start trigger input.
0 EXC The External Trigger Enable Bit.
EXC is set to allow the external CONVST pin be used as the active low convert start trigger input. When enabled, a
rising edge on this input pin trigger a conversion. This pin should remain low for a minimum pulse width of
100 nsec at the required sample rate.