Datasheet

ADuC814
Rev. A | Page 44 of 72
SERIAL PERIPHERAL INTERFACE
The ADuC814 integrates a complete hardware serial peripheral
interface (SPI) on-chip. SPI is an industry-standard synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and received simultaneously, i.e., full duplex. Note
that the SPI pins MISO and MOSI are multiplexed with digital
outputs P3.6 and P3.7. These pins are controlled via the CFG814.0
bit in the CFG814 SFR (Table 17), which configures the relevant
Port 3 pins for normal operation or serial port operation. When
the relevant Port 3 pins are configured for serial interface operation
via the CFG814 SFR, the SPE bit in the SPICON SFR configures
SPI or I
2
C operation (see SPE bit description in Table 18). SPI
can be configured for master or slave operation, and typically
consists of four pins described next.
MISO (Master In, Slave Out Data I/O Pin)
The MISO pin (Pin 23) is configured as an input line in master
mode and as an output line in slave mode. The MISO line on
the master (data in) should be connected to the MISO line in
the slave device (data out). The data is transferred as byte-wide
(8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI pin (Pin 24) is configured as an output line in master
mode and as an input line in slave mode. The MOSI line on the
master (data out) should be connected to the MOSI line in the
slave device (data in). The data is transferred as byte-wide (8-bit)
serial data, MSB first.
SCLOCK (Serial Clock I/O Pin)
The SCLOCK pin (Pin 25) is used to synchronize the data being
transmitted and received through the MOSI and MISO data
lines. A single data bit is transmitted and received in each
SCLOCK period. Therefore, a byte is transmitted/received after
eight SCLOCK periods. The SCLOCK pin is configured as an
output in master mode and as an input in slave mode.
In master mode, the bit rate, polarity, and phase of the clock are
controlled by the CPOL, CPHA, SPR0, and SPR1 bits in the
SPICON SFR (see Table 18). In slave mode, the SPICON register
must be configured with the phase and polarity (CPHA and
CPOL) of the expected input clock. In both master and slave
modes, the data is transmitted on one edge of the SCLOCK
signal and sampled on the other. It is important, therefore, that
the CPHA and CPOL are configured the same for the master
and slave devices.
SS
(Slave Select Input Pin)
The
SS
input pin (Pin 22) is used only when the ADuC814 is
configured in slave mode to enable the SPI peripheral. This line
is active low. Data is received or transmitted in slave mode only
when the
SS
pin is low, allowing the ADuC814 to be used in
single master, multislave SPI configurations. If CPHA = 1, then
the
SS
input may be permanently pulled low. With CPHA = 0,
the
SS
input must be driven low before the first bit in a byte-
wide transmission or reception and return high again after the
last bit in that byte-wide transmission or reception. In SPI slave
mode, the logic level on the external
SS
pin can be read via the
SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI interface.
SPICON SPI Control Register
SFR Address F8H
Power-On Default 04H
Bit Addressable Yes
ISPI WCOL SPE SPM CPOL CPHA SPR1 SPR0
Table 18. SPICON SFR Bit Designations
Bit No. Name Description
7 ISPI SPI Interrupt Bit.
Set by the MicroConverter at the end of each SPI transfer.
Cleared directly by the user code or indirectly by reading the SPIDAT SFR.
6 WCOL Write Collision Error Bit.
Set by the MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by the user.
5 SPE SPI Interface Enable Bit.
Set by the user to enable the SPI interface.
Cleared by the user to enable the I
2
C interface.
4 SPIM SPI Master/Slave Mode Select Bit.
Set by the user to enable master mode operation (SCLOCK is an output).
Cleared by the user to enable slave mode operation (SCLOCK is an input).
3 CPOL
1
Clock Polarity Select Bit.
Set by the user if SCLOCK idles high. Cleared by the user if SCLOCK idles low.