Datasheet

REV.
–53–
ADuC812
Parameter Min Typ Max Unit
SPI MASTER MODE TIMING (CPHA = 0)
t
SL
SCLOCK Low Pulsewidth 330 ns
t
SH
SCLOCK High Pulsewidth 330 ns
t
DAV
Data Output Valid after SCLOCK Edge 50 ns
t
DOSU
Data Output Setup before SCLOCK Edge 150 ns
t
DSU
Data Input Setup Time before SCLOCK Edge 100 ns
t
DHD
Data Input Hold Time after SCLOCK Edge 100 ns
t
DF
Data Output Fall Time 10 25 ns
t
DR
Data Output Rise Time 10 25 ns
t
SR
SCLOCK Rise Time 10 25 ns
t
SF
SCLOCK Fall Time 10 25 ns
t
DAV
MISO
MOSI
SCLOCK
(CPOL = 1)
SCLOCK
(CPOL = 0)
t
SH
t
SL
t
SR
t
SF
t
DOSU
t
DF
t
DR
t
DSU
t
DHD
MSB BIT 6–1 LSB
BIT 6–1
LSB IN
MSB IN
Figure 57. SPI Master Mode Timing (CPHA = 0)
F