Datasheet

REV.
ADuC812
–25–
Power Supply Monitor
PSMCON Control Register
SFR Address DFH
Power-On Default Value DCH
Bit Addressable No
—PMCIMSP2PT1PT0PTFSPNEMSP
Table X. PSMCON SFR Bit Designations
Bit Name Description
7 — Not Used.
6 CMP AV
DD
and DV
DD
Comparator Bit.
This is a read-only bit and directly reflects the state of the AV
DD
and DV
DD
comparators.
Read “1” indicates that both the AV
DD
and DV
DD
supplies are above their selected trip points.
Read “0” indicates that either the AV
DD
or DV
DD
supply is below its selected trip point.
5 PSMI Power Supply Monitor Interrupt Bit.
This bit will be set high by the MicroConverter if CMP is low, indicating low analog or digital
supply. The PSMI bit can be used to interrupt the processor. Once CMPD and/or CMP return
(and remain) high, a 256 ms counter is started. When this counter times out, the PSMI interrupt
is cleared. PSMI can also be written by the user. However, if either comparator output is low,
it is not possible for the user to clear PSMI.
4 TP2 V
DD
Trip Point Selection Bits.
3 TP1
2 TP0 These bits select the AV
DD
and DV
DD
trip point voltage as follows:
TP2 TP1 TP0 Selected DV
DD
Trip Point (V)
0 0 0 4.63
0 0 1 4.37
0 1 0 3.08
0 1 1 2.93
1 0 0 2.63
1 PSF AV
DD
/DV
DD
Fault Indicator.
Read “1” indicates that the AV
DD
supply caused the fault condition.
Read “0” indicates that the DV
DD
supply caused the fault condition.
0 PSMEN Power Supply Monitor Enable Bit.
Set to “1” by the user to enable the Power Supply Monitor Circuit.
Cleared to “0” by the user to disable the Power Supply Monitor Circuit.
Example
To configure the PSM for a trip point of 4.37 V, the following
code would be used:
MOV PSMCON,#005h ;enable PSM with
;4.37V threshold
SETB EA ;enable interrupts
MOV IE2,#002h ;enable PSM
;interrupt
If the supply voltage falls below this level, the PC would vector
to the ISR.
ORG 0043h ;PSM ISR
CHECK:MOV A,PSMCON ;PSMCON.5 is the
;PSM interrupt
;bit..
JB ACC.5,CHECK ;..it is cleared
;only when Vdd
;has remained
;above the trip
;point for 256ms
;or more.
RETI ; return only when "all's well"
SERIAL PERIPHERAL INTERFACE
The ADuC812 integrates a complete hardware Serial Peripheral
Interface (SPI) on-chip. SPI is an industry-standard synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and received simultaneously, i.e., full duplex. It should
be noted that the SPI pins are shared with the I
2
C interface, and
therefore the user can only enable one or the other interface at
any given time (see SPE in Table XI). The SPI Port can be con-
figured for Master or Slave operation and typically consists of
four pins, namely:
MISO (Master In, Slave Out Data I/O Pin)
The MISO (master in, slave out) pin is configured as an input
line in master mode and an output line in slave mode. The
MISO line on the master (data in) should be connected to the
MISO line in the slave device (data out). The data is transferred
as byte wide (8-bit) serial data, MSB first.
F