Datasheet

ADuC7128/ADuC7129
Rev. 0 | Page 9 of 92
Table 3. External Memory Read Cycle
Parameter Min Typ Max Unit
CLK 1/MD Clock ns typ × (CDPOWCON[2:0] + 1)
t
MS_AFTER_CLKH
4 8 ns
t
ADDR_AFTER_CLKH
4 16 ns
t
AE_H_AFTER_MS
½ CLK
t
AE
(XMxPAR[14:12] + 1) × CLK
t
HOLD_ADDR_AFTER_AE_L
½ CLK + (! XMxPAR[10] ) × CLK
t
RD_L_AFTER_AE_L
½ CLK + (! XMxPAR[10]+ ! XMxPAR[9] ) × CLK
t
RD_H_AFTER_CLKH
0 4 ns
t
RD
(XMxPAR[3:0] + 1) × CLK
t
DATA_BEFORE_RD_H
16 ns
t
DATA_AFTER_RD_H
8 + (! XMxPAR[9]) × CLK
t
RELEASE_WS_AFTER_RD_H
1 × CLK
0
6020-067
0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns
ECLK
GP0
AE
WS
RS
A/D[15:0]
BLE
BHE
XA16
FFFF 2348 XXXX CDEF XX 234A XX 89AB
CLK
t
AE_H_AFTER_MS
t
AE
t
HOLD_ADDR_AFTER_AE_L
t
RD_L_AFTER_AE_L
t
RD
t
RD_H_AFTER_CLKH
t
ADDR_AFTER_CLKH
t
RELEASE_WS_AFTER_RD_H
t
DATA_BEFORE_RD_H
t
DATA_AFTER_RD_H
SAMPLE_DATA_HSAMPLE_DATA_L
SAMPLE_ADDR_0
SAMPLE_ADDR_1
t
MS_AFTER_CLKH
Figure 4. External Memory Read Cycle